This collection of drawings and paintings presents a proposal for a ballroom dance center in Montreal, Quebec, Canada. The building is unnecessarily generous with the most essential elements and exaggerates non-essential elements in a way enhances their redundancy. Layered glulam ceilings cover the two main spaces and evoke the hidden structure of the sprung dance floor below. The ceiling is reflected in the pattern of the hardwood floors, and the ballroom is reflected in the pool outside its layered facade. Layers of concrete walls create thresholds and add depth to the views between spaces. Light, material, and people follow indirect paths through the building and its detailed elements. / Master of Architecture

As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed as viable alternatives to CMOS to tackle area and power issues. The power consumption can be minimized by the use of reversible logic instead of conventional combinational circuits. Theoretically, reversible circuits do not consume any power (or consume minimal power) when performing computations. This is achieved by avoiding information loss across the circuit. However, use of reversible circuits to implement digital logic requires development of new Electronic Design Automation techniques. Several approaches have been proposed and each method has its own pros and cons. This often results in multiple designs for the same function. Consequently, this demands research in efficient equivalence checking techniques for reversible circuits. This thesis explores the optimization and equivalence checking of reversible circuits. Most of the existing synthesis techniques work in two steps — generate an original, often sub-optimal, implementation for the circuit followed optimization of this design. This work proposes the use of Binary Decision Diagrams for optimization of reversible circuits. The proposed technique identifies repeated gate (trivial) as well as non-contiguous redundancies in a reversible circuit. Construction of a BDD for a sub-circuit (obtained by sliding a window of fixed size over the circuit) identifies redundant gates based upon the redundant variables in the BDD. This method was unsuccessful in identifying any additional redundancies in benchmark circuits; however, hidden non-contiguous redundancies were consistently identified for a family of randomly generated reversible circuits. As of now, several research groups focus upon efficient synthesis of reversible circuits. However, little work has been done in identification of redundant gates in existing designs and the proposed peephole optimization method stands among the few known techniques. This method fails to identify redundancies in a few cases indicating the complexity of the problem and the need for further research in this area. Even for simple logical functions, multiple circuit representations exist which exhibit a large variation in the total number of gates and circuit structure. It may be advantageous to have multiple implementations to provide flexibility in choice of implementation process but it is necessary to validate the functional equivalence of each such design. Equivalence checking for reversible circuits has been researched to some extent and a few pre-processing techniques have been proposed prior to this work. One such technique involves the use of Reversible Miter circuits followed by SAT-solvers to ascertain equivalence. The second half of this work focuses upon the application of the proposed reduction technique to Reversible Miter circuits as a pre-processing step to improve the efficiency of the subsequent SAT-based equivalence checking. / Master of Science

Yes / This article investigates the process of moving on from redundancy in the Welsh steel industry among individuals seeking new careers. It identifies a spectrum of career change experience, ranging from those who had actively planned their career change, prior to the redundancies, to those ‘at a career crossroads’, for whom there were tensions between future projects, present contingencies and past identities. It suggests that the process of moving on from redundancy can be better understood if we are able to identify, not just structural and cultural enablers and constraints but also the temporal dimensions of agency that facilitate or limit transformative action in the context of critical life events. Where individuals are located on the spectrum of career change experience will depend on the balance of enabling and constraining factors across the four aspects considered, namely temporal dimensions of agency, individuals’ biographical experience, structural and cultural contexts.

The amount of information that is churned out daily around the world is staggering, and hence, future technological advancements are contingent upon development of scalable acquisition, inference, and communication mechanisms for this massive data. This Ph.D. dissertation draws upon mathematical tools from information theory and statistics to understand the fundamental performance limits of universal compression of this massive data at the packet level using universal compression just above layer 3 of the network when the intermediate network nodes are enabled with the capability of memorizing the previous traffic. Universality of compression imposes an inevitable redundancy (overhead) to the compression performance of universal codes, which is due to the learning of the unknown source statistics. In this work, the previous asymptotic results about the redundancy of universal compression are generalized to consider the performance of universal compression at the finite-length regime (that is applicable to small network packets). Further, network compression via memory is proposed as a compression-based solution for the compression of relatively small network packets whenever the network nodes (i.e., the encoder and the decoder) are equipped with memory and have access to massive amounts of previous communication. In a nutshell, network compression via memory learns the patterns and statistics of the payloads of the packets and uses it for compression and reduction of the traffic. Network compression via memory, with the cost of increasing the computational overhead in the network nodes, significantly reduces the transmission cost in the network. This leads to huge performance improvement as the cost of transmitting one bit is by far greater than the cost of processing it.

The objective of this dissertation is to investigate both the theoretical and practical aspects of redundancy elimination methods in data networks. Redundancy elimination provides a powerful technique to improve the efficiency of network links in the face of redundant data. In this work, the concept of network compression is introduced to address the redundancy elimination problem. Network compression aspires to exploit the statistical correlation in data to better suppress redundancy. In a nutshell, network compression enables memorization of data packets in some nodes in the network. These nodes can learn the statistics of the information source generating the packets which can then be used toward reducing the length of codewords describing the packets emitted by the source. Memory elements facilitate the compression of individual packets using the side-information obtained from memorized data which is called ``memory-assisted compression''. Network compression improves upon de-duplication methods that only remove duplicate strings from flows. The first part of the work includes the design and analysis of practical algorithms for memory-assisted compression. These algorithms are designed based on the theoretical foundation proposed in our group by Beirami et al. The performance of these algorithms are compared to the existing compression techniques when the algorithms are tested on the real Internet traffic traces. Then, novel clustering techniques are proposed which can identify various information sources and apply the compression accordingly. This approach results in superior performance for memory-assisted compression when the input data comprises sequences generated by various and unrelated information sources. In the second part of the work the application of memory-assisted compression in wired networks is investigated. In particular, networks with random and power-law graphs are studied. Memory-assisted compression is applied in these graphs and the routing problem for compressed flows is addressed. Furthermore, the network-wide gain of the memorization is defined and its scaling behavior versus the number of memory nodes is characterized. In particular, through our analysis on these graphs, we show that non-vanishing network-wide gain of memorization is obtained even when the number of memory units is a tiny fraction of the total number of nodes in the network. In the third part of the work the application of memory-assisted compression in wireless networks is studied. For wireless networks, a novel network compression approach via memory-enabled helpers is proposed. Helpers provide side-information that is obtained via overhearing. The performance of network compression in wireless networks is characterized and the following benefits are demonstrated: offloading the wireless gateway, increasing the maximum number of mobile nodes served by the gateway, reducing the average packet delay, and improving the overall throughput in the network. Furthermore, the effect of wireless channel loss on the performance of the network compression scheme is studied. Finally, the performance of memory-assisted compression working in tandem with de-duplication is investigated and simulation results on real data traces from wireless users are provided.

The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response is estimated by fault tolerant technique. The purpose of the fault tolerant technique is to eliminate the need of standard response and enable online/real-time testing. Fault tolerant techniques use redundancy and majority voting to estimate the standard response. Redundancy in the circuit leads to fault aliasing. Fault aliasing misleads the majority voter in estimating the standard response. The statistics and phenomenon of aliasing are analyzed for benchmark circuits. The impact of fault aliasing on test with respect to coverage, test escape and over-kill is analyzed. The results show that aliasing can be detected with additional test vectors and get 100% fault coverage.

The problem of this study is whether between-channel redundancy in an instructional audio-visual message enhances immediate recall of information more than within—channel redundancy. A secondary purpose was to compare three forms of between—channel redundancy! audio—video, audio—video—caption, and audio-caption with one form of within-channel redundancy: video-caption. These comparisons were designed to demonstrate which form of redundancy had a higher association with recall of information. The subjects were administered the Kentucky Comprehensive Listening Inventory to measure listening skills, and the Receiver Apprehension Inventory to identify subjects who experienced significantly high apprehension as receivers of information. Then the subjects were randomly divided into four treatment groups and shown an eight minute newscast. All four groups were presented the same instructional message, but the mode of presentation differed depending upon the treatment group. After viewing the instructional program each member of each group was given a forty item multiple-choice retention inventory based on the information presented in the newscast. The data were presented in terms of correct responses on the Kentucky Comprehensive Listening Inventory and the forty item retention inventory. Discriminate analysis was used to determine which items from the multiple-choice retention inventory accounted for the most variance. Thirteen items were found to account for the greatest amount of variance. Reliability estimates were calculated for all four story categories and for the forty items collectively. All reliability estimates were acceptable.

The necessity for billions of parameters in large language models has lately been questioned as there are still unanswered questions regarding how information is captured in the networks. It could be argued that without this knowledge, there may be a tendency to overparametarize the models. In turn, the investigation of model redundancy and the methods which minimize it is important both to the academic and commercial entities. As such, the two main goals of this project were to, firstly, discover whether one of such methods, namely, distillation, reduces the redundancy of the language models without losing linguistic capabilities and, secondly, to determine whether the model architecture or multilingualism has a bigger effect on said reduction. To do so, ten models, both monolingual, multilingual, and their distilled counterparts, were evaluated layer and neuron-wise. In terms of layers, we have evaluated the layer correlation of all models by visualising heatmaps and calculating the average per layer similarity. For establishing the neuron-level redundancy, a classifier probe was applied on the model neurons, both the whole model and reduced by applying a clustering algorithm, and its performance was assessed for two tasks, Part-of-Speech (POS) and Dependency (DEP) tagging. To determine the distillation effects on the multilingualism of the models, we have investigated cross-lingual transfer for the same tasks and compared the results of the classifier as applied on multilingual models and one distilled variant in ten languages, nine Indo-European and one non-Indo-European. The results show that distillation reduces the number of redundant neurons at the cost of losing some of the linguistic knowledge. In addition, the redundancy in the distilled models is mainly attributed to the architecture on which it is based, with the multilingualism aspect having only a mild impact. Finally, the cross-lingual transfer experiments have shown that after distillation the model loses the ability to capture some languages more than others. In turn, the outcome of the project suggests that distillation could be applied to reduce the size of billion parameter models and is a promising method in terms of reducing the redundancy in current language models.

The use of robotic manipulators in industrial applications is continuously growing. Therefore, the proposal of novel kinematic architectures for robotic manipulators can be a strategy for coping with the required performance of specific tasks. On this matter, the parallel manipulators represent an alternative to fulfill this gap. The objective of this manuscript is to prove that the energy efficiency of parallel manipulators can be increased by the use of kinematic redundancy. Due to the presence of kinematic redundancy, the number of solutions to the inverse kinematics problem become infinite. Hence, a redundancy resolution scheme is required to select a suitable one among the infinite solutions. In this work, a model predictive control (MPC) based method is proposed as redundancy resolution scheme. This proposal is evaluated numerically and experimentally by comparing the energy consumption of non-redundant and kinematically redundant manipulators during the execution of pre-defined tasks. The non-redundant manipulator under study is the planar parallel 3RRR manipulator. This manipulator consists of three identical kinematic chains containing one active revolute joint and two passive revolute joints. Kinematic redundancies were added to the manipulator by including one active prismatic joint in each kinematic chain. In this way, the kinematically redundant manipulator under study is the planar parallel 3PRRR manipulator. By activating or locking the prismatic joints, up to three levels of kinematic redundancy can be evaluated. Numerical kinematic and dynamic models of the manipulators under study were derived not only for their numerical evaluation but also for the derivation of the model-based redundancy resolution scheme. Experimental data was acquired using the prototype built at the Laboratory of Dynamics at São Carlos School of Engineering at University of São Paulo. This experimental data was exploited for assessing the usability of the MPC for deriving a redundancy resolution scheme and for evaluating the impact of several levels of kinematic redundancy on the manipulator\'s energy consumption. Based on this data, one can conclude that MPC can be a suitable alternative for solve redundancy resolution problems and that the redundant parallel manipulators presented a lower energy consumption than the non-redundant one to execute the pre-defined tasks. The rate of reduction on the energy consumption achieved by the redundant manipulators varied between 6% and 60% depending on the task. Nevertheless, the numerical and experimental data presented differences in some particular cases. / O número de aplicações realizadas pelos manipuladores robóticos cresce continuamente. Assim, o desenvolvimento de novas arquiteturas para os manipuladores robóticos mais adaptadas a aplicações concretas é necessário. Destarte, os manipuladores paralelos constituem uma alternativa a ser considerada. O objetivo deste texto é provar que a eficiência energética dos manipuladores paralelos pode ser incrementada por meio da redundância cinemática. A presença de redundância cinemática implica um número infinito de soluções no problema da cinemática inversa. Logo, é precisso um esquema de resolução de redundância para escolher uma das soluções. No presente texto, um método baseado no modelo de controle preditivo (MPC), é proposto como esquema de resolução de redundância. Esta proposta é avaliada tanto numérica como experimentalmente comparando o consumo energético dos manipuladores não redundante e redundantes durante a execução de umas trajetórias predefinidas. O manipulador paralelo não redundante estudado é o 3RRR. Este manipulador é composto por três cadeias cinemáticas idênticas que incluem uma junta rotativa ativa e duas juntas rotativas passivas. Redundâncias cinemáticas foram adicionadas ao manipulador incluindo uma junta prismática ativa em cada uma das três cadeias cinemáticas, obtendo assim, o manipulador redundante 3PRRR. Ativando ou bloqueando as juntas prismáticas podem ser avaliados até três níveis de redundância cinemática. Modelos matemáticos dos manipuladores foram propostos tanto para a estabelecer uma avaliação numérica como para a dedução do esquema de resolução de redundância. Um protótipo do manipulador 3PRRR construído na Escola da Engenharia de São Carlos foi usado para realizar os experimentos. Os dados experimentais foram utilizados para comprovar a utilidade do MPC como esquema de resolução de redundância, e para avaliar os efeitos da redundância cinemática no consumo energético. Com fundamento nos resultados é possível concluir que o MPC pode ser uma alternativa adequada para resolver problemas de resolução de redundância e que os manipuladores paralelos redundantes apresentaram um menor consumo energético para realizar a mesma tarefa quando comparados aos não redundante. A taxa de redução da energia em favor dos manipuladores redundantes varia entre 6% e 60% dependendo da tarefa. Por outro lado, a análise numérica mostrou discrepâncias com a análise experimental em certas circunstâncias.

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates reduced-precision redundancy (RPR) as an effective and efficient alternative to the popular triple modular redundancy (TMR) for FPGA-based communications systems. Fault injection experiments show that RPR can improve the failure rate of a communications system by over 20 times over the unmitigated system at a cost less than half that of TMR by focusing on the critical SEUs. This dissertation contrasts the cost and performance of three different variations of RPR, one of which is a novel variation developed here, and concludes that the variation referred to as "Threshold RPR" is superior to the others for FPGA systems. Finally, this dissertation presents several methods for applying Threshold RPR to a system with the goal of reducing mitigation cost and increasing the system performance in the presence of SEUs. Additional fault injection experiments show that optimizing the application of RPR can result in a decrease in critical SEUs by as much 65% at no additional hardware cost.