Yes / A characteristic loop locus of dc power versus RF output power was observed as the frequency was varied around the optimum point of an operational active antenna. A new technique was introduced into the simulation, plotting the dependence of parameters such as supply current, efficiency or output power on internal impedance as seen by the naked transistor. It is now clear that the loop was formed as a consequence of the interaction of the transistor packaging elements with the patch impedances.

No description available.

Current AlGaN/GaN Heterojunction Field Effect Transistors (HFETs) make use of multiple sources, drains, and gates in parallel to maximize transconductance and effective gain while minimizing the current density through each channel. To connect the sources to a common ground, current practice prescribes the fabrication of air bridges above the gates and drains. This practice has the advantage of a low dielectric constant and low parasitic capacitance, but it is at the expense of manufacturability and robust device operation. In the study described below, the air bridges in AlGaN/GaN HFETs were replaced by a polymer supported metallization bridge with the intention of improving ease of fabrication and reliability. The DC, high frequency, and power performance for several polymer step heights were investigated. The resultant structures were functional and robust; however, their electrical performance was degraded due to high source resistance. The cause of the high source resistance was found to be thinning of the metallization at the polymer step. The effect was more pronounced for higher step heights. / Master of Science

yes / This paper describes the characterization and design of energy efficient user terminal transceiver power amplifier. To reduce the design of bulky external circuitry, the load modulation technique is employed. The design core is based on the combination of Class B and Class C that includes quarter wavelength transformer at the output to perform the load modulation. The handset transceiver for this power amplifier is designed to operate over the frequency range of 3.4GHz to 3.6GHz mobile WiMAX band. The performances of the load modulation amplifier are compared with conventional Class B amplifier. The results of 30dBm output power and 53% power added efficiency are achieved.

Yes / The biggest challenge for future 4G systems is the need to limit the energy consumptions of battery-powered and base station devices, with the aim to prolong their operational time and avoid active cooling in the base station. The green wireless communications requires research in areas such as energy efficient RF front end, MAC protocol, networking, deployment, operation, and also the integration of base station with renewable power supply. In this paper, the design concept of energy efficient RF front end is considered in terms of RF power amplifiers at which it represents the workhorse of modern wireless communication systems and inherently nonlinear. The approach of output power back off is to amplify the signal at the linear region to avoid distortion, but this approach suffers from significant reduction in efficiency and power output. To boost the efficiency at wide range of output power and keep the same margin for signal with high crest factor, the load modulation technique with new offset line are employed to operate over the frequency range of 3.4GHz to 3.6GHz band. The performances of load modulation power amplifier are compared with balanced amplifier. The results of 42dBm output power and 62% power added efficiency are achieved.

<p>The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. </p><p>In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current </p><p>The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.</p>

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width. In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor. Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Today, the silicon technology is well established for RF-applications (f~1-100 GHz), with emphasis on the lower frequencies (f &lt; 5 GHz). The field of RF power devices is extensive concerning materials and devices. One of the important RF-devices is the silicon LDMOS transistor. A large extent of the research presented in the thesis concerns studies of this device, which have resulted in increased understanding of the device behavior and improved performance. The thesis starts with a brief survey of the RF-field, including the LDMOS transistor, followed by a description of the methods used in the investigations; simulations, modeling and measurements. Specific results presented in the appended papers are also briefly summarized. A new concept for LDMOS transistors, which allows for both high frequency and high voltage operation, has been developed and characterized. World-record performance in terms of output power density was obtained: over 1 W/mm at 50 V and 3.2 GHz. Further understanding and improvements of the device are achieved using simulations and modeling. For determination of model parameters a new general parameter extraction technique was developed. The method has been successfully used for a large variety of high-frequency devices, and has been frequently used in the modeling work in this thesis. Important properties of RF-power devices are the device linearity and power efficiency. Extensive studies regarding the efficiency were conducted using numerical simulations and modeling of the off-state output resistance, which is correlated to the efficiency. The results show that significant improvements can be obtained for devices on both bulk- and SOI-substrates, using thin high-resistivity substrates and very low-resistivity SOI-substrates, respectively. Finally a new approach to drastically reduce substrate crosstalk by using very low-resistivity SOI substrate is proposed. Experimentally, a reduction of 20-40 dB was demonstrated in the GHz range compared to high-resistivity SOI substrate.

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

Linearity and efficiency are both critical parameters for radio frequency transmitter applications. In theory, a Doherty amplifier is a linear amplifier that is significantly more efficient than comparable conventional linear amplifiers. It comprises two amplifiers, connected at their outputs by a quarter-wave transformer. The main amplifier is always on, while the peaking amplifier is off during low power levels. Load modulation of the main amplifier occurs when the peaking amplifier is on due to the quarter-wave transformer, ensuring the main amplifier never enters saturation. This results in an efficiency characteristic that increases with respect to input power at twice the normal rate at low power levels, and plateaus to a high value at high power levels. However, in much of the research that has been done to-date, less-than-ideal results have been achieved (although efficiency was better than a conventional amplifier). It was decided to investigate the cause of the discrepancy between theoretical and practical results, and devise a method to counteract the problem. It was discovered that the main cause of the discrepancy was non-ideal transistor gate-voltage to drain-current characteristics. The implementation of a gate bias control scheme based upon measured transistor transfer characteristics, and the desired main and peaking amplifier output currents, resulted in a robust method to ensure near-ideal results. A prototype amplifier was constructed to test the control scheme, and theoretical, simulated and measured results were well matched. The amplifier had a region of high efficiency in the high power levels (over 34% for the last 6 dB of input power), and the gain was nearly constant with respect to input power (between 4 and 5 dB over the dynamic range). Furthermore, it was decided to investigate the role harmonics play within the Doherty amplifier. A classical implementation shunts unwanted harmonics to ground within the main and peaking amplifiers. However, odd harmonics generated by the peaking amplifier can be used to operate the main amplifier like a class F amplifier. This means its supply voltage can be lowered, without the amplifier entering saturation, and the efficiency of the Doherty amplifier can be increased without a detrimental effect on the its linearity. A prototype amplifier was constructed to test this theory, and gave good results, with better efficiency than that of a conventional amplifier, and a constant gain with respect to input power (between 6.4 dB and 6.5 dB over the dynamic range).