The use of neural networks, machine learning, or artificial intelligence, in its broadest and most controversial sense, has been a tumultuous journey involving three distinct hype cycles and a history dating back to the 1960s. Resurgent, enthusiastic interest in machine learning and its applications bolsters the case for machine learning as a fundamental computational kernel. Furthermore, researchers have demonstrated that machine learning can be utilized as an auxiliary component of applications to enhance or enable new types of computation such as approximate computing or automatic parallelization. In our view, machine learning becomes not the underlying application, but a ubiquitous component of applications. This view necessitates a different approach towards the deployment of machine learning computation that spans not only hardware design of accelerator architectures, but also user and supervisor software to enable the safe, simultaneous use of machine learning accelerator resources. In this dissertation, we propose a multi-transaction model of neural network computation to meet the needs of future machine learning applications. We demonstrate that this model, encompassing a decoupled backend accelerator for inference and learning from hardware and software for managing neural network transactions can be achieved with low overhead and integrated with a modern RISC-V microprocessor. Our extensions span user and supervisor software and data structures and, coupled with our hardware, enable multiple transactions from different address spaces to execute simultaneously, yet safely. Together, our system demonstrates the utility of a multi-transaction model to increase energy efficiency improvements and improve overall accelerator throughput for machine learning applications.

In recent years, developers have wanted to design more complex and advanced embedded processors. The feasibility of developed processors must be verified before the actual application. However, the process of verification always needs high costs and time. Quick Emulator (QEMU), a virtual platform emulator, can help in this situation. It can emulate different processors and hardware environments and build a unique platform according to the designers wishes. Many people have used QEMU to emulate advanced Reduced Instruction Set Computing (RISC) processors (like ARM) or the X86 architectures. Still, there is little research on RISC-V processors. Therefore, studying the QEMU to emulate the RISC-V processor is important. This thesis aims to evaluate the performance of the RISC-V processor using QEMU. Ten different benchmarks are designed, and their results are compared to reflect the performance of the RISC-V as well as the simulator. These results provide a reference when these benchmarks are run on the RISC-V processor that is on the actual hardware development board. / De senaste åren har utvecklarna alltid velat utveckla mer komplexa och avancerade funktioner på inbyggda utvecklingskort. Men de nya funktionerna måste verifieras innan man gör kretskortet. Å andra sidan så kostar verifieringsprocessen mycket tid och pengar. Quick Emulator (QEMU), en virtuell plattformsemulator, kan hjälpa till för att lösa detta problem. Den kan emulera olika processorer och hårdvarumiljöer och bygga en unik plattform allt enligt designernas önskemål. Många människor har använt QEMU för att emulera avancerade Reduced Instruction Set Computing (RISC)-processorer (som ARM), eller X86-arkitekturerna, men det finns mycket lite forskning om RISC-V processorer. Därför är det viktigt att studera QEMU för att emulera RISC-V-processorn. Denna avhandling syftar till att utvärdera prestandan för RISC-V processorer genom att använder QEMU. Tio olika benchmarks konstrueras för att användas för att spegla prestandan hos processorn såväl som simulatorn. Dessa resultat kan sedan användas som referens när benchmarken körs på de RISC-V-processorer som finns på det aktuella hårdvaruutvecklingskortet.

This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.

Deep Learning and Neural Networks have been studied and developed for many years as of today, but there is still a great need of research on this field, because the industry needs are rapidly changing. The new challenge in this field is called edge inference and it is the deployment of Deep Learning on small, simple and cheap devices, such as low-power microcontrollers. At the same time, also on the field of hardware design the industry is moving towards the RISC-V micro-architecture, which is open-source and is developing at such a fast rate that it will soon become the standard. A batteryless ultra low power microcontroller based on energy harvesting and RISC-V microarchitecture has been the final target device of this thesis. The challenge on which this project is based is to make a simple Neural Network work on this chip, i.e., finding out the capabilities and the limits of this chip for such an application and trying to optimize as much as possible the power and energy consumption. To do that TensorFlow Lite Micro has been chosen as the Deep Learning framework of reference, and a simple existing application was studied and tested first on the SparkFun Edge board and then successfully ported to the RISC-V ONiO.zero core, with its restrictive features. The optimizations have been done only on the convolutional layer of the neural network, both by Software, implementing the Im2col algorithm, and by Hardware, designing and implementing a new RISC-V instruction and the corresponding Hardware unit that performs four 8-bit parallel multiply-and-accumulate operations. This new design drastically reduces both the inference time (3.7 times reduction) and the number of instructions executed (4.8 times reduction), meaning lower overall power consumption. This kind of application on this type of chip can open the doors to a whole new market, giving the possibility to have thousands small, cheap and self-sufficient chips deploying Deep Learning applications to solve simple everyday life problems, even without network connection and without any privacy issue. / Deep Learning och neurala nätverk har studerats och utvecklats i många år fram till idag, men det finns fortfarande ett stort behov av forskning på detta område, eftersom industrins behov förändras snabbt. Den nya utmaningen inom detta område kallas edge inferens och det är implementeringen av Deep Learning på små, enkla och billiga enheter, såsom lågeffektmikrokontroller. Samtidigt, även på området hårdvarudesign, går industrin mot RISC-V-mikroarkitekturen, som är öppen källkod och utvecklas i så snabb takt att den snart kommer att bli standarden. En batterilös mikrokontroller med ultralåg effekt baserad på energiinsamling och RISC-V-mikroarkitektur har varit den slutliga målenheten för denna avhandling. Utmaningen som detta projekt är baserat på är att få ett enkelt neuralt nätverk att fungera på detta chip, det vill säga att ta reda på funktionerna och gränserna för detta chip för en sådan applikation och försöka optimera så mycket som möjligt ström- och energiförbrukningen. För att göra det har TensorFlow Lite Micro valts som referensram för Deep Learning, och en enkel befintlig applikation studerades och testades först på SparkFun Edge-kortet och portades sedan framgångsrikt till RISC-V ONiO.zero-kärnan, med dess restriktiva funktioner. Optimeringarna har endast gjorts på det konvolutionerande skikt av det neurala nätverket, både av mjukvara, implementering av Im2col-algoritmen, och av hårdvara, design och implementering av en ny RISC-V-instruktion och motsvarande hårdvaruenhet som utför fyra 8-bitars parallella multiplikation -och-ackumulationsoperationer. Denna nya design minskar drastiskt både slutledningstiden (3,7 gånger kortare) och antalet utförda instruktioner (4.8 gånger färre), vilket innebär lägre total strömförbrukning. Den här typen av applikationer på den här typen av chip kan öppna dörrarna till en helt ny marknad, vilket ger möjlighet att ha tusentals små, billiga och självförsörjande chip som distribuerar Deep Learning-applikationer för att lösa enkla vardagsproblem, även utan nätverksanslutning och utan någon integritetsproblematik.

Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.

The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.

The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.