Made available in DSpace on 2014-12-17T14:55:12Z (GMT). No. of bitstreams: 1 LeonardoAC_TESE.pdf: 2904145 bytes, checksum: 71e85899a3f895d52ccee194769fd506 (MD5) Previous issue date: 2013-07-11 / In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments / No meio acad?mico, ? comum a cria??o de processadores denominados did?ticos, voltados para pr?ticas de disciplinas de hardware na ?rea de Computa??o e que podem ser utilizados como plataformas em disciplinas de softwares, sistemas operacionais e compiladores. Muitas vezes, tais processadores s?o descritos sem uma ISA padr?o, o que exige a cria??o de compiladores e outros softwares b?sicos para prover a interface hardware/software dificultando sua integra??o com outros processadores e demais dispositivos. Utilizar dispositivos reconfigur?veis descritos em uma linguagem do tipo HDL permitem a cria??o ou modifica??o de qualquer componente da microarquitetura, ocasionando a altera??o das unidades funcionais do caminho de dados que representa a parte operativa de um processador, bem como da m?quina de estados que implementa a unidade de controle do mesmo conforme surgem novas necessidades. Em particular, os processadores RISP possibilitam a altera??o das instru??es da m?quina, permitindo inserir ou modificar instru??es, podendo at? mesmo se adaptar a uma nova arquitetura. Este trabalho aborda como objeto de estudo dois processadores did?ticos soft-core descritos em VHDL com diferentes n?veis de complexidade de hardware adaptados a uma ISA padr?o a partir de uma metodologia proposta sem provocar aumento no n?vel de complexidade do hardware, ou seja, sem o acr?scimo significativo da ?rea em chip, ao mesmo tempo em que o seu n?vel de desempenho na execu??o de aplica??es permanece inalterado ou ? aprimorado. As modifica??es tamb?m permitem afirmar que, al?m de ser poss?vel substituir a arquitetura de um processador sem alterar sua organiza??o, um processador RISP pode alternar entre diferentes conjuntos de instru??o, o que pode ser expandido para altern?ncia entre diferentes ISAs, permitindo a um mesmo processador se tornar uma arquitetura h?brida adaptativa, pass?vel de ser utilizada em sistemas embarcados e ambientes multiprocessados heterog?neos

Made available in DSpace on 2014-12-17T15:48:05Z (GMT). No. of bitstreams: 1 LeonardoAC.pdf: 6046620 bytes, checksum: ad9a9332aa6ef3e81e83f93b75f55894 (MD5) Previous issue date: 2006-05-19 / The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed / A Computa??o Reconfigur?vel ? uma solu??o intermedi?ria na resolu??o de problemas complexos, possibilitando combinar a velocidade do hardware com a flexibilidade do software. Uma arquitetura reconfigur?vel possui v?rias metas, entre estas o aumento de desempenho. Dentre os v?rios segmentos em rela??o ?s arquiteturas reconfigur?veis, destacam-se os Processadores Reconfigur?veis. Estes processadores combinam as fun??es de um microprocessador com uma l?gica reconfigur?vel e podem ser adaptados depois do processo de desenvolvimento. Processadores com Conjunto de Instru??es Reconfigur?veis (RISP -Reconfigurable Instruction Set Processors) s?o um subconjunto dos processadores reconfigur?veis, que visa como meta a reconfigura??o do conjunto de instru??es do processador, envolvendo caracter?sticas referentes aos padr?es de instru??es como formatos, operandos, e opera??es elementares. Este trabalho possui como objetivo principal o desenvolvimento de um processador RISP, combinando as t?cnicas de configura??o do conjunto de instru??es do processador executadas em tempo de desenvolvimento, e de reconfigura??o do mesmo em tempo de execu??o. O projeto e implementa??o em VHDL deste processador RISP tem como intuito provar a aplicabilidade e a efici?ncia de dois conceitos: utilizar mais de um conjunto de instru??o fixo, com apenas um ativo em determinado momento, e a possibilidade de criar e combinar novas instru??es, de modo que o processador passe a reconhec?-las e utiliz?-las em tempo real como se estas existissem no conjunto de instru??o fixo. A cria??o e combina??o de instru??es ? realizada mediante uma unidade de reconfigura??o incorporada ao processador. Esta unidade permite que o usu?rio possa enviar instru??es customizadas ao processador para que depois possa utiliz?-las como se fossem instru??es fixas do processador. Neste trabalho tamb?m encontram-se simula??es de aplica??es envolvendo instru??es fixas e customizadas e resultados das compara??es entre estas aplica??es em rela??o ao consumo de pot?ncia e ao tempo de execu??o que confirmam a obten??o das metas para as quais o processador foi desenvolvido

Ce manuscrit présente les travaux menés pour proposer un flot de conception permettant d’implanter des processeurs RISP dans un circuit reprogrammable (FPGA). Après une description des différentes solutions envisageables pour réaliser des prototypes dans le domaine du traitement d’image, ce document décrit une méthode qui consiste à générer des modèles matériels de processeurs destinés au traitement d’images, avec des opérateurs taillés sur une application donnée. Un ensemble d’expérimentations utilisant des algorithmes courants permet d’évaluer les performances du flot de conception proposé. Le prototypage rapide d’un système biométrique sans contact, basé sur la reconnaissance de paumes a été aussi réalisé sur la plateforme de test. / This manuscript presents work to propose a development cycle to establish RISP processors in a reprogrammable chip (FPGA). After a description of the various possible solutions to produce image processing prototypes, this document describes a method which consists in generating hardware models of processor target to image processing, with operators just for a given application. Test with a set of common algorithm makes evaluate the performances of the design cycle proposed. Rapid prototyping of a contact less biometric system, based on palmprint recognition, is also realized on the test platform.

Ce manuscrit présente les travaux menés pour proposer un flot de conception permettant d'implanter des processeurs RISP dans un circuit reprogrammable (FPGA). Après une description des différentes solutions envisageables pour réaliser des prototypes dans le domaine du traitement d'image, ce document décrit une méthode qui consiste à générer des modèles matériels de processeurs destinés au traitement d'images, avec des opérateurs taillés sur une application donnée. Un ensemble d'expérimentations utilisant des algorithmes courants permet d'évaluer les performances du flot de conception proposé. Le prototypage rapide d'un système biométrique sans contact, basé sur la reconnaissance de paumes a été aussi réalisé sur la plateforme de test.

Chez Arabidopsis, la protéine RISP est détournée par le virus CaMV pour assurer, ensemble avec la protéine virale TAV, la traduction de son ARN polycistronique. RISP a été identifiée comme une cible de la voie de signalisation de TOR et il a été montré que sa phosphorylation est requise pour promouvoir la réinitiation de la traduction activée par TAV. Les résultats que j’ai obtenus suggèrent que RISP, lorsqu’elle n’est pas phosphorylée, intervient ensemble avec eIF3, au niveau du complexe de pré-initiation 43S pour recruter le complexe ternaire grâce à l’interaction entre RISP et la sous-unité b du facteur eIF2. Il s’est avéré que RISP a la capacité, lorsqu’elle est phosphorylée, d’interagir non seulement avec la protéine ribosomique eL24 mais également avec eS6. Nos résultats indiquent que la liaison entre les sous-unités ribosomiques 60S et 40S sous l’effet de RISP, est régulée par la voie de TOR et qu’elle joue un rôle important dans le contrôle de la réinitiation de la traduction. / Many factors are required to recruit the tRNAi and a 60S ribosomal subunit to the 40S ribosomal subunit preinitiation complex. This recruitment is normally strictly limited during reinitiation of translation if factors recruited during the primary translation event are shed from 40S. However, factor retention can occur during long ORF translation if the CaMV viral factor TAV is present. RISP is a downstream target of TOR and found either within the 43S preinitiation complex, if bound to eIF3, and/or attached to 60S, if phosphorylated by TOR. We show here that RISP interacts with subunit b of eIF2 before phosphorylation. Critically, TOR activation up-regulates phosphorylation of both RISP and eS6 as well as the binding of both factors. Importantly, eS6-deficient plants are less active in TAV-mediated reinitiation and are thus less susceptible to CaMV infection. It is attractive to propose that eS6 phosphorylation contributes to retention and re-use of 60S during 40S scanning.