Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Document formatted into pages; contains xv, 128 p.; also includes graphics (some col.). Includes bibliographical references (p. 125-128). Available online via OhioLINK's ETD Center

Cheng Wang Chi. / "October 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 135-139) / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

The determination of the optimal location of transceivers is a critical design factor when deploying a wireless local area network (WLAN). The performance of the WLAN will improve in a variety of aspects when the transceivers' locations are adequately determined, including the overall cell coverage to the battery life of the client units. Currently, the most common method to determine the appropriate location of transceivers is known as a site survey, which is normally a very time and energy consuming process. The main objective of this research was to improve current methodologies for the optimal or near-optimal placement of APs in a WLAN installation. To achieve this objective, several improvements and additions were made to an existing computational tool to reflect the evolution that WLAN equipment has experienced in recent years. Major additions to the computational tool included the addition of the capability to handle multiple power levels for the transceivers, the implementation of a more adequate and precise representation of the passive interference sources for the path loss calculations, and the definition of a termination criterion to achieve reasonable computational times without compromising the quality of the solution. An experiment was designed to assess how the improvements made to the computational tool provided the desired balance between computational time and the quality of the solutions obtained. The controlled factors were the level of strictness of the termination criterion (i.e., high or low), and the number of runs performed (i.e., 1, 5, 10, 15, and 20 runs). The low level of strictness proved to dramatically reduce (i.e., from 65 to 70%) the running time required to obtain an acceptable solution when compared to that obtained at the high level of strictness. The quality of the solutions found with a single run was considerably lower than that obtained with the any other number of runs. On the other hand, the quality of the solutions seemed to stabilize at and after 10 runs, indicating that there is no added value to the quality of the solution when 15 or 20 runs are performed. In summary, having the computational tool developed in this research execute 5 runs with the low level of strictness would generate high quality solutions in a reasonable running time. / Graduation date: 2004

Roy A. Paananen. / "September 22, 1952." "Based on a thesis presented for the degree of Electrical Engineer, Massachusetts Institute of Technology, 1952." / Bibliography: p. 84-85. / Army Signal Corps Contract DA36-039 sc-100, Project 8-102B-0. Dept. of the Army Project 3-99-10-022.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Cressler, John; Committee Member: Gerhardt, Rosario; Committee Member: Ingram, Mary Ann; Committee Member: Papapolymerou, John; Committee Member: Shen, Shyh-Chiang. Part of the SMARTech Electronic Thesis and Dissertation Collection.

In downlink multi-user multiple-input multiple-output (MU-MIMO) systems, different users, even multiple data streams serving one user, might require different quality-of-services (QoS). The transceiver should allocate resources to different users aiming at satisfying their QoS requirements. In order to design the optimal transceiver, channel state information is necessary. In practice, channel state information has to to be estimated, and estimation error is unavoidable. Therefore, robust transceiver design, which takes the channel estimation uncertainty into consideration, is important. For the previous robust transceiver designs, bounded estimation errors or Gaussian estimation errors were assumed. However, if there exists unknown distributed interference, the distribution of the channel estimation error cannot be modeled accurately a priori. Therefore, in this thesis, we investigate the robust transceiver design problem in downlink MU-MIMO system under probabilistic QoS constraints with arbitrary distributed channel estimation error. To tackle the probabilistic QoS constraints under arbitrary distributed channel estimation error, the transceiver design problem is expressed in terms of worst-case probabilistic constraints. Two methods are then proposed to solve the worst-case problem. Firstly, the Chebyshev inequality based method is proposed. After the worst-case probabilistic constraint is approximated by the Chebyshev inequality, an iteration between two convex subproblems is proposed to solve the approximated problem. The convergence of the iterative method is proved, the implementation issues and the computational complexity are discussed. Secondly, in order to solve the worst-case probabilistic constraint more accurately, a novel duality method is proposed. After a series of reformulations based on duality and S-Lemma, the worst-case statistically constrained problem is transformed into a deterministic finite constrained problem, with strong duality guaranteed. The resulting problem is then solved by a convergence-guaranteed iteration between two subproblems. Although one of the subproblems is still nonconvex, it can be solved by a tight semidefinite relaxation (SDR). Simulation results show that, compared to the non-robust method, the QoS requirement is satisfied by both proposed algorithms. Furthermore, among the two proposed methods, the duality method shows a superior performance in transmit power, while the Chebyshev method demonstrates a lower computational complexity. / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012

The objective of the proposed research is to develop simplified reconfigurable transmission systems with frequency multipliers for the transmission of complex modulated signals. Because they rely on nonlinear properties, frequency multiplier-based transmission systems require proper linearization techniques and accurate modeling of the signal transfer function. To accomplish these two goals, the author has developed techniques to model and linearize frequency multipliers and to digitize feedback signals for nonlinear characterization. First, adaptive predistortion techniques and zonal transfer theories have been developed for modeling and linearization. The predistortion system has been verified by applying an IS-95B signal to various frequency multipliers built by the author. Second, because the output signals at higher harmonic zones occupy wider frequency bandwidths than the signal in the fundamental zone does and thus make it harder to use traditional sampling techniques, a simplified but effective method called the sub-Nyquist sampling rate was developed and verified. Third, two methods for reconfigurable transmitters using frequency multipliers in conjunction with digital predistortion linearizers were developed. Both methods make it possible to transmit complex signals via frequency multipliers by using dual-band transmission systems that incorporate frequency multipliers that are based on linearization techniques. One of these methods uses a circuit topology that can be switched between a fundamental-mode in-phase combined amplifier and a push-push frequency doubler using input phasing. The second suggested method uses a fundamental-frequency power amplifier followed by a varactor multiplier that can be bypassed with an RF switch. This work will contribute to the development of low-cost and size-effective reconfigurable transmission systems because it requires fewer transmitting components and needs less sampling of the feedback networks.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy