Le travail présenté dans ce manuscrit a été effectué au sein de l’équipe de microélectronique de l’Institut de Recherche sur les lois Fondamentales de l’Univers (IRFU) du CEA. Il s’inscrit dans le contexte de la spectro-imagerie X et gamma pour la recherche en Astrophysique. Dans ce domaine, les futures expériences embarquées à bords de satellites nécessiteront des instruments d’imagerie à très hautes résolutions spatiales et énergétiques.La résolution spectrale d’une gamma-camera est dégradée par l’imperfection du détecteur lors de l’interaction photon-matière lui-même et par le bruit électronique. Si on ne peut réduire l’imprécision de conversion photon-charge du détecteur, on peut minimiser le bruit apporté par l’électronique de lecture. L’objectif de cette thèse est la conception d’une électronique intégrée de lecture de détecteur semi-conducteurs CdTe pixélisés pour gamma-caméra(s) compacte(s) et aboutable(s) sur 4 côtés à résolution spatiale « Fano limitée ». Les objectifs principaux de ce circuit intégré sont: un très bas bruit pour la mesure d’énergie des rayons-X, une très basse consommation, et une taille de canal de détection adaptée au pas des pixels CdTe. Pour concevoir une telle électronique, chaque paramètre contribuant au bruit doit être optimisé. L’hybridation entre l’électronique de lecture et le détecteur est également un paramètre clef qui fait généralement la résolution finale de l’instrument : en imposant une géométrie matricielle à l’ASIC adaptée au pas de 300 µm des pixels de CdTe, on peut espérer, réduire d’un facteur 10 la capacité parasite amenée par la connexion détecteur-électronique et améliorer d’autant le bruit électronique tout en conservant une densité de puissance constante. Une bonne connaissance des propriétés du détecteur nous permet alors d’extraire ses paramètres électroniques clefs pour concevoir l’architecture électronique de conversion et de filtrage optimale. Dans le cadre de cette thèse j’ai conçu deux circuits intégrés en technologies CMOS XFAB 0.18 µm. Le premier, Caterpylar, est destiné à caractériser cette nouvelle technologie, y compris en radiation, identifier un étage d’entrée pour le pixel adapté au détecteur, et valider par la mesure les résultats théoriques établis sur deux architectures de filtrage, semi gaussien et « Multi-Correlated Double Sampling » (MCDS), approchant l’efficacité du filtrage optimal et adaptées aux applications finales. Le deuxième circuit, D2R1, est un système complet, constitué de 256 canaux de lecture de détecteur CdTe, organisés dans une matrice de 16×16 pixels. Chaque canal comprend un préamplificateur de charge adapté à des pixels de 300 μm×300 μm, un opérateur de filtrage de type MCDS de profondeur programmable, d’un discriminateur auto-déclenché à bas seuil de détection programmable par canal. L’ASIC a été caractérisé sans détecteur et est en voie d’être hybridé à une matrice de CdTe très prochainement. Les résultats de caractérisations de la puce nue, en particulier en terme de produit puissance × bruit, sont excellents. La consommation de la puce est de 315 µW/ canal, la charge équivalente de bruit mesurée sur tous les canaux est de 29 électrons rms. Ces résultats valident le choix d’intégration d’un filtrage de type MCDS, qui est, à notre connaissance une première mondiale pour la lecture de détecteurs CdTe. Par ailleurs, ils nous permettent d’envisager d’excellentes résolutions spectrales de l’ensemble détecteur+ASIC, de l’ordre de 600 eV FWHM à 60 keV. / The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l’Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit.In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit. related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF - 1 pF and a dark current below 5 pA.In the frame of this thesis I have designed two ASICs. The first one, Caterpylar, is a testchip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D2R1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16×16 array. Each channel fits into a layout area of 300 μm × 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW⁄channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV.

No description available.

This thesis reports the development of high performance readout electronics for resistive microbolometer detector arrays that are used for uncooled infrared imaging. Three different readout chips are designed and fabricated by using a standard 0.6 &micro / m CMOS process. Fabricated chips include a conventional capacitive transimpedance amplifier (CTIA) type readout circuit, a novel readout circuit with dynamic resistance nonuniformity compensation capability, and a new improved version of the CTIA circuit. The fabricated CTIA type readout circuit uses two digital-to-analog converters (DACs) with multiple analog buses which compensate the resistance nonuniformity by adjusting the bias currents of detector and reference resistors. Compensated detector current is integrated by a switched capacitor integrator with offset cancellation capability followed by a sample-and-hold circuit. The measured detector referred current noise is 47.2 pA in an electrical bandwidth of 2.6 KHz, corresponding to an expected SNR of 530. The dynamic nonuniformity compensation circuit uses a feedback structure that dynamically changes the bias currents of the reference and detector resistors. A special feature of the circuit is that it provides continuous compensation for the detector and reference resistances due to temperature changes over time. Test results of the fabricated circuit show that the circuit reduces the offset current due to resistance nonuniformity 42.5 times. However, the calculated detector referred current noise is 360 pA, which limits the circuit SNR to 70. The improved CTIA type readout circuit introduces a new detector biasing method by using an additional auxiliary biasing transistor for better current controllability. The improved readout circuit alleviates the need for high resolution compensation DACs, which drastically decreases the circuit area. The circuit occupies an area of one seventh of the first design. According to test results, the current compensation ratio is 170, and the detector referred current noise is 48.6 pA in a 2.6 KHz bandwidth.

No description available.

In preparation for the High-Luminosity Large Hadron Collider (HL-LHC) at CERN, the Compact Muon Solenoid (CMS) Detector is undergoing a series of upgrades to its existing infrastructure, and is adding in several completely new subdetector systems. The first of these new systems, called GE1/1, is a series of 144 gas electron multiplier (GEM) detectors, arranged as 36 two-detector "superchambers" in each of the muon endcaps of CMS. These detectors are a subtype of micropattern gas detectors, and consist of three layers of "GEM foils", thin sheets of polyimide coated with 5 um of copper on each side and chemically etched with holes of 50 - 70 um diameter at a pitch of 140 um. These layers are stacked on top of a printed circuit board (PCB) readout and sealed within a gastight volume that is filled with Ar:CO2 70:30, and a high voltage is applied to the foils to create electric fields within the GEM detectors. When a muon enters the detector and ionizes the gas within, the ionized electrons encounter these fields and multiply in Townsend avalanches at each successive foil layer, until they are read out at the readout PCB at a gain of ~10^4. In early 2017, a demonstrator system known as the "slice test" was installed into the negative endcap. Consisting of 10 GEM detectors, the two-year-long slice test served as both a proof of concept for the GE1/1 system and an invaluable learning experience that would permanently impact not only the GE1/1 project, but future GEM systems GE2/1 and ME0 as well. During the slice test, it was observed that readout channels were being lost in the course of operation to such a degree that the operational lifetime of the system was in serious jeopardy. These losses were attributed to damage to the front-end readout ASIC (VFAT) inputs, caused propagating electrical discharges within the detectors, and a dedicated campaign to study the discharges was launched. The results of this study will be presented in this dissertation. A campaign to mitigate these discharges and their resulting damage was launched. In order to protect the sensitive VFAT from damage, several external protection circuits were proposed and thoroughly tested. The results of these tests, which are presented herein, determined that a series of resistors totaling 470 Ohms would be installed on the VFAT hybrid. When coupled with an additional 200 kOhm resistor on the HV filter, this reduced the probability of damage following a discharge from 93% to 3% As GE2/1 and ME0 are not due to be installed for another few years, more complex discharge-prevention measures can be put into place. As such, the following measures have been examined, and results will be discussed herein: A new, larger VFAT hybrid is being manufactured, whose larger surface area can accommodate more robust protection circuits than those considered and used for GE1/1. As well, double-segmented GEM foils, in which both the top and bottom of each foil is segmented into < 100 cm^2 sectors that are separated by resistors, were examined for use in the detectors. These double-segmented foils were found to introduce a cross-talk signal in the detectors that results in false signals being treated as true signals, which causes a saturation of the GEM bandwidth and results in unwanted dead time. These cross-talk signals, as well as the compromises made to reduce the cross-talk while maintaining robust discharge prevention, will be discussed. / Doctorat en Sciences / info:eu-repo/semantics/nonPublished

This thesis presents the development of integrated readout electronics for diode type microbolometers and development of external camera electronics for microbolometers. The developed readout electronics are fabricated with its integrated 160x120 resolution FPA (Focal Plane Array) in the XFAB SOI-CMOS 1.0 &mu / m process. The pixels in the FPA have 70 &mu / m pixel pitch, and they are sensitive in the 8&ndash / 12 &mu / m band of the infrared spectrum. Each pixel has 4 serially connected diodes, and diode turn on voltage changes as the temperature of the suspended and thermally isolated pixel increases due to the absorbed infrared power. Suspension of the pixels is obtained with a post-CMOS MEMS etching process, but this process requires no critical litography and/or deposition steps. This dramatically reduces the detector process cost, which makes this microbolometer FPA suitable for ultra low-cost applications such as automobile, security, and commercial applications. The readout electronics of the FPA include digital blocks such as timing and programming blocks as well as analog blocks such as a differential trans-conductance amplifier, a switched capacitor integrator, a sampleand- hold, and current DACs. This new readout design has reduced number of pins to simplify the external electronics and allows wafer-level vacuum packaging compared to the 128x128 FPA developed in a previous study at METU with the same approach. Both of these features further decrease the cost. Two kinds of external camera electronics are developed for two SOI type microbolometers. The first one is for the 128x128 SOI microbolometer previously designed in METU. The developed external camera electronics have 1.5mVrms noise, which is much less than the microbolometer noise. The overall system has an average NETD of 465 mK and a peak NETD of 320mK. The second developed external camera electronics are for the 160x120 SOI microbolometers that developed in the scope of this thesis. The developed external camera electronics has 0.55mVrms noise which is much less than the bolometer noise which is 5mVrms. The overall system has an average NETD of 820 mK and a peak NETD of 350 mK. Each of these external camera electronics include a custom designed PCB, an FPGA board with appropiate configurion and a software working on a PC. The custom designed PCB holds the external components for the microbolometer, an FPGA takes and processes the bolometer data and it sends to a PC, and a PC processes these data and forms a streaming video. These two external camera electronics allow to obtain human images verifying that the developed microbolometers can be used for security and automotive applications.

<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible. A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector. The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

Die laufenden Aufrüstungsarbeiten des Large Hadron Colliders haben das Ziel, die Luminosität der Teilchenkollisionen zu erhöhen. Die erhöhte Luminosität liefert zwar neue Möglichkeiten für Präzisionsmessungen und Teilchensuchen, stellt aber gleichzeitig eine große Herausforderung an die beteiligten Experimente. Aus diesem Grund wird auch der ATLAS-Detektor aufgerüstet. Der Fokus ist dabei, eine hohe Effizienz des Triggers sicherzustellen, der die interessanten Physikereignisse in Echtzeit auswählt. Dafür wird das Flüssig-Argon-Kalorimeter des ATLAS-Detektors mit einer neuen Ausleseelektronik ausgerüstet. Um die Funktionsfähigkeit zu testen, wurde ein Demonstrationsaufbau der zukünftigen Ausleseelektronik installiert und von 2014 bis 2018 parallel zur ATLAS- Datennahme betrieben. In dieser Arbeit werden die Daten, die mit dem Aufbau aufgezeichnet wurden, analysiert. Die neue Ausleseelektronik erlaubt es, komplexere Algorithmen zur Erkennung von Signal- und Untergrundereignissen zu nutzen. Es handelt sich dabei um Variablen zur Beschreibung der Form von elektromagnetischen und hadronischen Teilchenschauern im Flüssig-Argon-Kalorimeter. Die Effizienz dieser Variablen wird untersucht. Dabei wird nach Kombination mehrerer Variablen eine Untergrundunterdrückung hadronischer Jets von 75 % bei einer Elektronenerkennungseffizienz von 90 % erreicht. Die zukünftige, erhöhte Luminosität führt dazu, dass sich bei Teilchenkollisionen die Zahl der Ereignisse, die sich sowohl zeitlich als auch räumlich überlappen, erhöht. Der Effekt dieser Überlappereignisse hat Auswirkungen auf die Energierekonstruktion. Daher wird eine Untersuchung der Überlappereignisse durchgeführt, um eine möglichst genaue Kenntnis über diese zu erhalten. Für die Rekonstruktion aus den Signalen der im Detektor deponierten Energie stehen verschiedene digitale Signalfilter zur Auswahl. Die Performanz hinsichtlich der Signalerkennung dieser Algorithmen wird überprüft. Es zeigt sich, dass neue digitale Signalfilter zwar den Effekt des zeitlichen Überlapps von Detektorpulsen reduzieren, jedoch sehr sensitiv auf die genaue Pulsmodellierung sind. / The ongoing upgrade activities at the Large Hadron Collider aim for an increase of the luminosity in the particle collisions. The increased luminosity delivers new capabilities for precision measurements and searches for signatures of new physics. At the same time, challenges arise for the experiments. For this reason, the ATLAS detector is upgraded. The focus is on maintaining the high efficiency of the trigger that selects interesting physics events in real-time. Therefore, the Liquid-Argon calorimeter of the ATLAS detector is upgraded with new readout electronics. To evaluate the performance, a demonstrator readout was installed and operated in parallel to the data taking of the main readout between 2014 and 2018. In this thesis, the data recorded with the demonstrator is analyzed. The new readout electronics allow more sophisticated algorithms to distinguish between signal and background events. They are based on variables that describe electromagnetic and hadronic showers. The proposed shower-shape variables are studied concerning their trigger efficiency and background rejection power. With a combination of the shower-shape variables, a background rejection power of 75 % for hadronic jets is achieved while keeping the electron trigger efficiency at 90 %. The increase in luminosity will lead to an increase in in-time and out-of-time pile-up effects. These have an impact on the energy reconstruction. Therefore, pile-up events are investigated, to gain precise knowledge about their effects. For the energy reconstruction of the detector signals, different digital filter algorithms are available. The signal detection efficiency of these algorithms is examined. While new filter algorithms are capable of reducing the effect of out-of-time pile-up, they depend greatly on the correct phase of the pulse shape.

El Laboratori d'Altes Energies de La Salle és un membre d'un grup acreditat per la Generalitat. Aquest grup està format per part del Departament d'Estructura i Constituents de la Matèria de la Facultat de Física de la Universitat de Barcelona, part del departament d'Electrònica de la mateixa Facultat i pel grup de La Salle. Tots ells estan involucrats en el disseny d'un subdetector en l'experiment de LHCb del CERN: el SPD (Scintillator Pad Detector). El SPD és part del Calorímetre de LHCb. Aquest sistema proporciona possibles hadrons d'alta energia, electrons i fotons pel primer nivell de trigger. El SPD està format per una làmina centellejeadora de plàstic, dividida en 600 cel.les de diferent tamany per obtenir una millor granularitat aprop del feix. Les partícules carregades que travessin el centellejador generaran una ionització del mateix, a diferència dels fotons que no la ionitzaran. Aquesta ionització, generarà un pols de llum que serà recollit per una WLS que està enrotllada dins de les cel.les centellejadores. La llum serà transmesa al sistema de lectura mitjançant fibres clares. Per reducció de costos, aquestes 6000 cel.les estan dividides en grups, usant MAPMT (fotomultiplicadors multiànode) de 64 canals per rebre la informació en el sistema de lectura. El senyal de sortida dels fotomultilplicadors és irregular degut al baix nivell de fotoestadística, uns 20-30 fotoelectrons per MIP, i degut també a la resposta de la fibra WLS, que té un temps de baixada lent. Degut a tot això, el processat del senyal, es realitza primer durant la integració de la càrrega total i finalment per la correcció de la cua que conté el senyal provinent del PMT. Aquesta Tesi està enfocada en el sistema de lectura de l'electrònica del VFE del SPD. Aquest, està format per un ASIC (dissenyat pel grup de la UB) encarregat d'integrar el senyal, compensar el senyal restant i comparar el nivell d'energia obtingut amb un llindar programable (fa la distinció entre electrons i fotons), una FPGA que programa aquests llindars i compensacions de cada ASIC i fa el mapeig de cada canal rebut en el detector i finalment usa serialitzadors LVDS per enviar la informació de sortida al trigger de primer nivell. En el disseny d'aquest tipus d'electrònica s'haurà de tenir en compte, per un costat, restriccions de tipus mecànic: l'espai disponible per l'electrònica és limitat i escàs, i per un altre costat, el nivell de radiació que deurà suportar és considerable i s'haurà de comprobar que tots els components superin un cert test de radiació, i finalment, també s'haurà de tenir en compte la distància que separa els VFE dels racks on la informació és enviada i el tipus de senyal amb el que es treballa en aquest tipus d'experiments: mixta i de poc rang. / El Laboratorio de Altas Energías de la Salle es un miembro de un grupo acreditado por La Generalitat. Este grupo está formado por parte del departamento de Estructura i Constituents de la Matèria de la Facultad de Física de la Universidad de Barcelona, parte del departamento de Electrónica de la misma Facultad y el grupo de La Salle. Todos ellos están involucrados en el diseño de un subdetector en el experimento de LHCb del CERN: El SPD (Scintillator Pad Detector). El SPD es parte del Calorímetro de LHCb. Este sistema proporciona posibles hadrones de alta energía, electrones y fotones para el primer nivel de trigger.El SPD está diseñado para distinguir entre electrones y fotones para el trigger de primer nivel. Este detector está formado por una lámina centelleadora de plástico, dividida en 6000 celdas de diferente tamaño para obtener una mejor granularidad cerca del haz. Las partículas cargadas que atraviesen el centelleador generarán una ionización del mismo, a diferencia de los fotones que no la generarán. Esta ionización generará, a su vez, un pulso de luz que será recogido por una WLS que está enrollada dentro de las celdas centelleadoras. La luz será transmitida al sistema de lectura mediante fibras claras. Para reducción de costes, estas 6000 celdas están divididas en grupos, utilizando un MAPMT (fotomultiplicadores multiánodo) de 64 canales para recibir la información en el sistema de lectura. La señal de salida de los fotomultiplicadores es irregular debido al bajo nivel de fotoestadística, unos 20-30 fotoelectrones por MIP, y debido también a la respuesta de la fibra WLS, que tiene un tiempo de bajada lento. Debido a todo esto, el procesado de la señal, se realiza primero mediante la integración de la carga total y finalmente por la substracción de la señal restante fuera del período de integración. Esta Tesis está enfocada en el sistema de lectura de la electrónica del VFE del SPD. Éste, está formado por un ASIC (diseñado por el grupo de la UB) encargado de integrar la señal, compensar la señal restante y comparar el nivel de energía obtenido con un umbral programable (que distingue entre electrones y fotones), y una FPGA que programa estos umbrales y compensaciones de cada ASIC, y mapea cada uno de los canales recibidos en el detector y finalmente usa serializadores LVDS para enviar la información de salida al trigger de primer nivel. En el diseño de este tipo de electrónica se deberá tener en cuenta, por un lado, restricciones del tipo mecánico: el espacio disponible para la electrónica en sí, es limitado y escaso, por otro lado, el nivel de radiación que deberá soportar es considerable y se tendrá que comprobar que todos los componentes usado superen un cierto test de radiación, y finalmente, también se deberá tener en cuenta la distancia que separa los VFE de los racks dónde la información es enviada y el tipo de señal con el que se trabaja en este tipo de experimentos: mixta y de poco rango. / Laboratory in La Salle is a member of a Credited Research Group by La Generatitat. This group is formed by a part of the ECM department, a part of the Electronics department at UB (University of Barcelona) and La Salle's group. Together, they are involved in the design of a subdetector at LHCb Experiment at CERN: the SPD (Scintillator Pad Detector). The SPD is a part of LHCb Calorimeter. That system provides high energy hadrons, electron and photons candidates for the first level trigger. The SPD is designed to distinguish electrons and photons for this first level trigger. This detector is a plastic scintillator layer, divided in about 6000 cells of different size to obtain better granularity near the beam. Charged particles will produce, and photons will not, ionisation on the scintillator. This ionisation generates a light pulse that is collected by a Wavelength Shifting (WLS) fibre that is twisted inside the scintillator cell. The light is transmitted through a clear fibre to the readout system. For cost reduction, these 6000 cells are divided in groups using a MAPMT of 64 channels for receiving information in the readout system. The signal outing the SPD PMTs is rather unpredictable as a result of the low number of photostatistics, 20-30 photoelectrons per MIP, and the due to the response of the WLS fibre, which has low decay time. Then, the signal processing must be performed by first integrating the total charge and later subtracting to avoid pile-up. This PhD is focused on the VFE (Very Front End) of SPD Readout system. It is performed by a specific ASIC (designed by the UB group) which integrates the signal, makes the pile-up compensation, and compares the level obtained to a programmable threshold (distinguishing electrons and photons), an FPGA which programs the ASIC thresholds, pile-up subtraction and mapping the channels in the detector and finally LVDS serializers, in order to send information to the first level trigger system. Not only mechanical constraints had to be taken into account in the design of the card as a result of the little space for the readout electronics but also, on one hand, the radiation quote expected in the environment and on the other hand, the distance between the VFE electronics and the racks were information is sent and the signal range that this kind of experiments usually have.