A área de robótica móvel se encontra numa fase de grande expansão, mas um dos obstáculos a ser vencido é o desenvolvimento de sistemas computacionais embarcados que combinem baixo consumo de energia com alta capacidade de processamento. A computação reconfigurável tem o potencial para atender esta demanda. Este trabalho visa avaliar as dificuldades no aproveitamento desta tecnologia através da implementação em hardware de um sistema de desvio de obstáculos para robôs móveis usando uma única câmera de baixo custo como sensor. Normalmente os algorítmos de fluxo óptico usados neste projeto são implementados inteiramente em software e sofrem várias restrições para poderem operar nos computadores embarcados nos robôs. O projeto descrito neste trabalho não tem estas restrições mas exige um esforço maior de desenvolvimento / The area of mobile robotics is undergoing a tremendous expansion, but one of the obstacles to be dealt with is the development of embedded computational systems that combine low power consumption and high performance. Reconfigurable computing has the potential to meet these requirements. This project is an evaluation of the complexities of fully exploiting this technology through the hardware implementation of an obstacle avoidance system for mobile robots using a single, low cost camera as its sensor. Normally, the optic flow algorithms used in this project are implemented entirely in software and so suffer several limitations in order to run on computers embedded in the robots. The hardware described here does not have the same limitations but requires more development effort

O presente trabalho apresenta a implementação de um core de rede Ethernet 10/100Mbps com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. A tecnologia Ethernet foi implementada em computação reconfigurável e utilizou-se como base um módulo disponível na Internet denominado OpenCores MAC 10/100. O projeto foi desenvolvido para ser aplicado em sistemas embarcados, mais especificamente para o uso em um robô móvel em desenvolvimento no Laboratório de Computação Reconfigurável do ICMC/USP. O core foi incorporado à biblioteca da ferramenta SoPC Builder da Altera, visando uma fácil integração do mesmo em outros projetos. Foram utilizadas as ferramentas Quartus II e ModelSim para o desenvolvimento e testes do sistema, além de dois kits Nios versão Stratix para a validação do projeto, sendo as placas interligadas ponto-a-ponto sem a utilizaçao de transceivers analógicos. / This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tool’s library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers.

Este trabalho apresenta a construção de um sistema embarcado para detectar pedestres, utilizando computação reconfigurável com captura de imagens através de uma única câmera acoplada a um veículo que trafega em ambiente urbano. A principal motivação é a necessidade de reduzir o número vítimas causadas por acidentes de trânsito envolvendo pedestres. Uma das causas está relacionada com a velocidade de resposta do cérebro humano para reconhecer situações de perigo e tomar decisões. Como resultando, há um interesse mundial de cientistas para elaborar soluções economicamente viáveis que venham a contribuir com inovações tecnológicas direcionadas a auxiliar motoristas na condução de veículos. A implementação em hardware deste sistema foi desenvolvida em FPGA e dividida em blocos interconectados. Primeiramente, no pré-tratamento do vídeo, foi construído um bloco para conversão de dados da câmera para escala de cinza, em seguida, um bloco simplificado para a estabilização vertical dinâmica de vídeo. Para a detecção foram construídos dois blocos, um para detecção binária de movimento e um bloco de detecção BLOB. Para fazer a classificação, foi construído um bloco para identificação do tamanho do objeto em movimento e fazendo a seleção pela proporcionalidade. Os testes em ambiente real deste sistema demonstraram ótimos resultados para uma velocidade máxima de 30 km/h / This work proposes an embedded system to detect pedestrians using reconfigurable computing making the image acquisition through a mono-camera attached to a vehicle in an urban environment. This work is motivated by the need to reduce the number of traffic accidents, even with government support, each year hundreds of people become victims thus bringing great damage to the economy. As a result, there is also a global concern of scientists to promote economically viable solutions that will contribute to reducing these accidents. A significant issue is related to the speed of response of the human brain to recognize and or to make decisions in situations of danger. This feature generates a demand for technological solutions aimed at helping people to drive vehicles in several respects. The system hardware was developed in FPGA and divided into interconnected blocks. First, for the pretreatment of the video, was built a block for data conversion from the camera to grayscale, then a simplified block for vertical stabilization dynamic video. To detection, two blocks were built, one for binary motion detection and one for a BLOB detection. To classify, was built one block to identify the size of the object in motion by the proportionality and making the selection. The tests in real environment of this system showed great results for a maximum speed of 30 km / h

Embedded devices permeate our every day lives. They exist in our vehicles, traffic lights, medical equipment, and infrastructure controls. In many cases, improper functionality of these devices can present a physical danger to their users, data or financial loss, etc. Improper functionality can be a result of software or hardware bugs, but now more than ever, is often the result of malicious compromise and tampering, or as it is known colloquially "hacking". We are beginning to witness a proliferation of cyber-crime, and as more devices are built with internet connectivity (in the so called "Internet of Things"), security should be of the utmost concern. Embedded devices have begun to seamlessly merge with our daily existence. Therefore the need for security grows as it more directly affects the safety of our data, property, and even physical health. This thesis presents an FPGA-assisted framework for remote attestation, a security service that allows a remote device to prove to a verifying entity that it can be trusted. In other words, it presents a protocol by which a device (be it an insulin pump, vehicle, etc.) can prove to a user (or other entity) that it can be trusted - i.e. that it has not been "hacked". This is accomplished through executable code integrity verification and run-time monitoring. In essence, the protocol verifies that a device is running authorized and untampered software and makes it known to a verifier in a trusted fashion. We implement the protocol on a physical device to demonstrate its feasibility and to examine its performance impact.

Conventionally, to speed up scientific or engineering (S&E) computation programs on general-purpose computers, one may elect to use faster CPUs, more memory, systems with more efficient (though complicated) architecture, better software compilers, or even coding with assembly languages. With the emergence of Field Programmable Gate Array (FPGA) based Reconfigurable Computing (RC) technology, numerical scientists and engineers now have another option using FPGA devices as core components to address their computational problems. The hardware-programmable, low-cost, but powerful “FPGA-enhanced computer” has now become an attractive approach for many S&E applications. A new computer architecture model for FPGA-enhanced computer systems and its detailed hardware implementation are proposed for accelerating the solutions of computationally demanding and data intensive numerical PDE problems. New FPGAoptimized algorithms/methods for rapid executions of representative numerical methods such as Finite Difference Methods (FDM) and Finite Element Methods (FEM) are designed, analyzed, and implemented on it. Linear wave equations based on seismic data processing applications are adopted as the targeting PDE problems to demonstrate the effectiveness of this new computer model. Their sustained computational performances are compared with pure software programs operating on commodity CPUbased general-purpose computers. Quantitative analysis is performed from a hierarchical set of aspects as customized/extraordinary computer arithmetic or function units, compact but flexible system architecture and memory hierarchy, and hardwareoptimized numerical algorithms or methods that may be inappropriate for conventional general-purpose computers. The preferable property of in-system hardware reconfigurability of the new system is emphasized aiming at effectively accelerating the execution of complex multi-stage numerical applications. Methodologies for accelerating the targeting PDE problems as well as other numerical PDE problems, such as heat equations and Laplace equations utilizing programmable hardware resources are concluded, which imply the broad usage of the proposed FPGA-enhanced computers.

<p> </p><p>Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain.</p><p>As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server.</p>

Field Programmable Gate Arrays (FPGAs) support the reconfigurable computing paradigm by providing an integrated circuit hardware platform that facilitates software like reconfigurability. The addition of an embedded microprocessor and peripherals to traditional FPGA Combinational Logic Blocks (CLBs) interleaved with interconnections has effectively resulted in a programmable system on-chip. FPGAs are used to support flexible implementations of Application Specific Integrated Circuit (ASIC) functions. Because FPGAs are reconfigurable, they often are used in place of ASICs during the cicuit design process. FPGAs are also used when only a small number of ICs are required: ASICs necessitate large manufacturing runs to be economically viable; for smaller runs the use of FPGAs is an economic alternative. Application domains of interest, such as intelligent guidance systems, medical devices, and sensors, often require low power, inexpensive calculation of trance- dental functions. COordinate Rotation DIgital Computer (CORDIC) is an iterative algorithm used to emmulate hardware expensive multipliers, such as Multiply/ACculmulate (MAC) units, with only shift and add operations. However, because CORDIC is a sequential algorithm, characterized as having the latency of a serial multiplier, techniques that speed up computational performance have many applications.To this end, three implementations of standard CORDIC, (i) unrolled hardwired, (ii) unrolled programmable, and (iii) rolled programmable, were implemented on four Xilinx FPGA families: Virtex-4, -5, and -6, and Spartan-6. Although hardwired unrolled was found to have the greatest speed at the expense of no runtime flexibility, and rolled programmable was found to have the greatest flexibility and lowest silicon area consumption at the expense of the longest propagation delay, improvements to CORDIC implementations were still sought. Three parallelized CORDIC techniques, P-CORDIC, Flat-CORDIC, and Para-CORDIC, were implemented on the same four FPGA families. P-CORDIC and Flat-CORDIC, were shown to have the lowest latency under various conditions; Para-CORDIC was found to perform well in deeply pipelined, high throughput circuits. Design rules for when to use standard versus precomputation CORDIC techniques are presented. To address the low power requirements of many applications of interest, the Unfolded Multiplexor-LRB (UMUX-LRB), patent held by Sima, et al, was analyzed in weak inversion across four transistor technology nodes (180nm, 130nm, 90nm, and 65nm). Previous was also expanded from strong inversion across 180nm, 130nm, and 90nm technology nodes to also include 65nm. The UMUX-LRB interconnection network is based upon the Xilinx commercial interconnection network. Therefore, this network (MUX-LRB), and another static circuit technique, CMOS-Transmission Gates (CMOS-TG), were profiled across all four technology nodes to provide a baseline of comparision. This analysis found the UMUX-LRB to have the smallest and most balanced rising and falling edge propagation delay, in addition to having the greatest reliability for temperature and process variation. / Graduate

The ubiquity of Internet connectivity means there is a greater need for computer network safety and security. Cost-effective secure computing networks and broadband applications not only need a sophisticated cryptosystem to accelerate data encryption, but also need substantial computational power to handle large data streams. Reconfigurable System-on-Chip (rSoC) technology is well suited to accelerate network cryptographic applications by implementing the entire computing application on a single reconfigurable chip. Hardware-software co-design and hardware-software communication are some key questions involved in using this rSoC technology. This thesis investigates how best to accelerate a cryptographic application using rSoC technology. Some background on FPGAs, reconfigurable computing, inter-process communication methods, hardware/software co-design, cryptography in general, and 3DES in particular are firstly introduced. Some existing reconfigurable computing systems and 3DES implementations on FPGA are then reviewed and analyzed. A new general hardware-software architecture, which consists of a CPU, memories, customized peripherals and buses on a single FPGA chip, is designed to accelerate the security application. The 3DES application is divided into four functional modules: input, subkey generation, data processing, and output modules. Shared memory with semaphores is chosen for the inter-module communication. A complete inter-module communication solution is presented for hardware and software module communications. A generic component, HWCOM, is designed for those communications which involve hardware modules. Experimental results show that using two buffers as shared memories between communication modules and increasing shared memory size are good methods for transferring data between hardware/software modules more efficiently. When investigating the best hardware/software partition scheme, all 3DES modules are first executed in software on the FPGA. The experimental results of 83Kbps encryption throughput indicate that the software-only solution is not satisfactory. Through profiling, the bottleneck is shown to be the data processing module and the subkey generation module, which are then implemented in hardware. Experimental results show an improved 179Mbps throughput. This presents over 2000 times acceleration compared to software and shows that the hardware-software co-implementation can efficiently accelerate the 3DES application with good performance and flexibility.

Estudar as propriedades físicas do solo envolve conhecer a umidade, o transporte de água e solutos, a densidade, a identificação da porosidade, o que é essencial para o crescimento de raízes das plantas. Para esses estudos, a tomografia de raios X tem se mostrado uma técnica útil. As imagens tomográficas são obtidas através de projeções (sinais) que são reconstruídos com algoritmos adequados. No processo de aquisição dessas projeções, podem surgir ruídos provenientes de diferentes fontes. O sinal tomográfico apresenta ruídos que possuem uma distribuição de Poisson gerada pela contagem de fótons, bem como o detector de fótons é influenciado por uma presença de ruído eletrônico com uma distribuição Gaussiana. Essas diferentes distribuições podem ser mapeadas com transformadas não lineares específicas que alteram uma distribuição Gaussiana para outros tipos de distribuições, como a de transformada de Anscombe (Poisson) ou transformada de Box-Muller (Uniforme), mas são aproximações que apresentam erros acumulativos. As transformadas podem ser então mapeadas por um sistema de redes neurais, o que garante um melhor resultado com o filtro de Kalman não linear em que os pesos da rede e as medidas das projeções são estimados em conjunto. Este trabalho apresenta uma nova solução com filtragem de Kalman descentralizada utilizando redes neurais artificiais embarcada em uma arquitetura reconfigurável com o intuito de obter se um valor ótimo de melhoria na relação Sinal/Ruído de projeções tomográficas e consequentemente nas imagens reconstruídas proporcionando melhorias para os métodos de análise dos físicos de solos agrícolas. / To study the physical properties of soil moisture involves knowing the transport of water and solutes, density, porosity identification, which is essential for the growth of plant roots. For these studies, X-ray tomography has been shown to be a useful technique. The tomographic images are obtained through projections (signals) that are reconstructed with appropriate algorithms. In the process of acquiring these projections, noise can arise from different sources. The tomographic signal is noisy which have a Poisson distribution generated by photon counting, and the photon detector is influenced by a presence of electronic noise with a Gaussian distribution. These different distributions can be mapped to specific nonlinear transformed altering a Gaussian distribution for other types of distributions, such as the Anscombe transform (Poisson) or Box-Muller transform (Uniform), but are approximations that have cumulative errors. Transforms can then be mapped by a neural network system, which ensures a better result with nonlinear Kalman filter in which the network weights and measures of the projections are estimated together. This work presents a new solution to the unscented Kalman filtering using artificial neural networks embedded in a reconfigurable architecture in order to obtain an optimum value of improvement in S/N ratio of tomographic projections and consequently the images reconstructed by providing improvements for the methods of physical parameters of the agricultural soils.

A área de robótica móvel se encontra numa fase de grande expansão, mas um dos obstáculos a ser vencido é o desenvolvimento de sistemas computacionais embarcados que combinem baixo consumo de energia com alta capacidade de processamento. A computação reconfigurável tem o potencial para atender esta demanda. Este trabalho visa avaliar as dificuldades no aproveitamento desta tecnologia através da implementação em hardware de um sistema de desvio de obstáculos para robôs móveis usando uma única câmera de baixo custo como sensor. Normalmente os algorítmos de fluxo óptico usados neste projeto são implementados inteiramente em software e sofrem várias restrições para poderem operar nos computadores embarcados nos robôs. O projeto descrito neste trabalho não tem estas restrições mas exige um esforço maior de desenvolvimento / The area of mobile robotics is undergoing a tremendous expansion, but one of the obstacles to be dealt with is the development of embedded computational systems that combine low power consumption and high performance. Reconfigurable computing has the potential to meet these requirements. This project is an evaluation of the complexities of fully exploiting this technology through the hardware implementation of an obstacle avoidance system for mobile robots using a single, low cost camera as its sensor. Normally, the optic flow algorithms used in this project are implemented entirely in software and so suffer several limitations in order to run on computers embedded in the robots. The hardware described here does not have the same limitations but requires more development effort