This master thesis goes into problematics of design of an electronic device control system and its realization. First of all its overall conception is specified and potential hardware platforms are analyzed afterwards. Based on this analysis the system’s final conception is drawn up, the device’s circuit layout is created and finally a functional prototype is manufactured. The later part of this thesis describes the software accessories and tools. The principles of a chosen operating system, management application and webbased interface are described along with the problems of authentization to solve. The proposed solutions for the authentization-specific tasks gave rise to the final implementation of the authentization methods and techniques.

At the end of 70th of last century the concept began to emerge, now is referred as a cryptographic hash function. Currently, these functions are associated especially with a digital signature. In 2005, the worldwide most used function SHA-1 was broken. This fact led in 2007 NIST announced a public competition to create a new secure hash algorithm. This Thesis deals with issues of cryptographic hash functions from the beginning of their theoretical formulation to current events in this area. Key words: Cryptographic hash functions, SHA-1, MD5, NIST competition

The tendency of recent years towards electrification of aircraft components and subsys-tems has opened the door for a wider usability of electro-mechanical actuators (EMAs) inthat context. EMAs are already in use in aircraft industries but mainly in civil aviation forsecondary control systems and non-critical applications. Therefore it is evident that thereexists a need for further research in the sector of utilization of EMAs for other areas withinthe aircraft manufacturing industry before they can be effectively applied. In this thesisan analysis of the power and thermal behaviour of EMAs has been done to evaluate theirapplicability in primary control systems for fighter aircrafts as compared to conventionallyused hydraulic systems. Furthermore, a method for scaling of such actuators in an initialdesign stage where few parameters are known has been developed and validated. One ofthe most substantial drawbacks against choosing EMAs for these purposes is the disadvan-tageous thermal transfer capability of electrical machines in high power applications. Aninvestigation has therefore also been made on calculation of power losses of electrical mo-tors and inverters. The results have been compared against a servo hydraulic actuator. Ascalable simulation model derived from motor data statistics has been developed in orderto simulate power losses and the thermal behaviour of these actuators. The model takesvery few parameters as input as an aircraft designer working in the preliminary stages ofthe design process often have limited knowledge of the final product, but at the same timeneed a fairly accurate view of how the actuators ought to be scaled with regard to weight,power and thermal transfer. The model shows promising results when verified against anactual electro-mechanical actuator on Iron Bird test rig. Finally, this work aims to furtherthe development of an Iron Bird situated on Linköping University, through an integrationbetween three thesis projects where the final product shall be an Hardware In The Loop(HWIL) simulation with several actuators involved.

Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard (SHA-1, SHA2) and for carry-less multiplication. These crypto-instructions are optimized for a single algorithm and provide significant performance improvements over software written using general-purpose instruction set. However, today's secure systems and protocols do not rely on just one, but a suite of many cryptographic applications that are expected to work in a correct and reliable manner. In this work, we propose a new instruction set for supporting efficient and reliable cryptography on modern processors. For efficiency, we propose flexible instruction set extensions for Keccak, a cryptographic kernel for hashing, authenticated encryption, key-stream generation and random-number generation. Keccak is the basis of the SHA-3 standard and the newly proposed Keyak and Ketje authenticated ciphers. For reliability, we propose a set of trusted instructions to verify the integrity of a cryptographic software library. These instructions are aimed at detecting tamper in the software or in the configurable hardware. We develop the instruction extensions for a 128-bit interface, commonly available in the vector processing unit of many modern processors. Simulation results on GEM5 architectural simulator show that the proposed instructions not only improves the performance of Keccak applications by 2 times (over NEON programming) and 6 times (over assembly programming), but also improves the reliability of applications at a performance overhead of just 6%. / Master of Science

While 5G energy harvesting makes 5G smart dust possible, stretching computation across power cycles affects cryptographic algorithms. This effect may lead to new security issues that make the system vulnerable to adversary attacks. Therefore, security measures are needed to protect data at rest and in transit across the network. In this paper, we identify the security requirements of existing 5G networks and the best-of-breed cryptographic algorithms for ultra-low SWaP devices in an energy harvesting context. To do this, we quantify the performance vs. energy tradespace, investigate the device features that impact the tradespace the most, and assess the security impact when the attacker has access to intermediate results. Our open-source energy-harvesting-tolerant versions of the cryptographic algorithms provide algorithm and device recommendations and ultra-low SWaP energy-harvesting-device-optimized versions of the cryptographic algorithms. / Master of Science / Smart dust is a network of tiny and energy-efficient devices that can gather data from the environment using various sensors, such as temperature, pressure, and humidity sensors. These devices are extremely small, often as small as a grain of sand or smaller, and have numerous applications, including environmental monitoring, structural health monitoring, and military surveillance. One of the main challenges of smart dust is its small size and limited energy resources, making it challenging to power and process the collected data. However, advancements in energy harvesting and low-power computing are being developed to overcome these challenges. In the case of 5G, energy harvesting technologies can be used to power small sensors and devices that are part of the 5G network, such as the Internet of Things (IoT) devices. Examples of IoT devices are wearable fitness trackers, smart thermostats, security cameras, home automation systems, and industrial sensors. Since 5G energy harvesting impacts the daily lives of people using the relevant devices, our research seeks to find out what kind of measures are necessary to guarantee their security.

published_or_final_version / abstract / Urban Design / Master / Master of Urban Design

The rise of the Internet of Things (IoT) and autonomous robots/vehicles comes with a lot of embedded electronic systems. Small printed circuit boards with microcomputers will be embedded almost everywhere. Therefore, the security and data protection of those systems will be a significant challenge to take into consideration for the future development of IoT devices. Cryptographic algorithms can be used to provide confidentiality and integrity for data transmitted between those embedded devices. It is important to know what kind of algorithm is the most suitable for the specified task and the selected embedded device.  In this thesis, several commonly used cryptographic algorithms are evaluated and an EPS32 based IoT device is chosen as the evaluation platform. ESP32 is a series of low cost and low power System-on-Chip microcontrollers with integrated Wi-Fi and dual-mode Bluetooth. Additionally, ESP32 has the hardware acceleration feature for commonly used cryptographic algorithms. The goal of this thesis is to evaluate the performances of different cryptographic algorithms on the ESP32 with and without using the hardware acceleration feature. The execution times of different cryptographic algorithms processing data with varying sizes are collected, and the performance of each cryptographic algorithm is then evaluated.  A data logging scenario is evaluated as a case study where the ESP32 periodically sends data to a remote database. Under different configurations of the ESP32, the transmission time of encrypted and non-encrypted communications via Hypertext Transfer Protocol Secure (HTTPS) and Hypertext Transfer Protocol (HTTP) will be compared.  The results can be used to simplify the calculation of performance/protection trade-offs for specific algorithms. It also shows that the built-in hardware acceleration has a significant impact on increasing those algorithms’ performances. For Advanced Encryption Standard (AES), the throughput for encryption increased by 257.8%, and for decryption 222.7%. For Secure Hash Algorithm (SHA-2), the throughput increased by 165.2%. For Rivest-Shamir-Adleman (RSA), the encryption throughput has a decrease of 40.7%, and decryption has an increase of 184%. Furthermore, the results can also aid the design and development of a secure IoT system incorporating devices built with ESP32. / Uppkomsten av Internet of Things (IoT) och autonoma robotar / fordon kommer med många inbyggda elektroniska system. Små kretskort med mikrodatorer kommer att vara inbäddade nästan överallt. Därför kommer säkerheten och dataskyddet för dessa system att vara en betydande utmaning att ta hänsyn till för den framtida utvecklingen av IoT-enheter. Kryptografiska algoritmer kan användas för att ge sekretess och integritet för data som överförs mellan de inbäddade enheterna. Det är viktigt att veta vilken typ av algoritm som är bäst lämpad för den angivna uppgiften och den valda inbäddade enheten.  I denna avhandling utvärderas flera vanliga kryptografiska algoritmer och en EPS32-baserad IoT-enhet väljs som utvärderingsplattform. ESP32 är en serie av låga och lågeffektiva system-on-chip-mikrokontroller med integrerat Wi-Fi och dual-mode Bluetooth. Dessutom har ESP32 hårdvaruaccelereringsfunktionen för vanliga kryptografiska algoritmer. Målet med denna avhandling är att utvärdera prestanda för olika kryptografiska algoritmer på ESP32 med och utan att använda hårdvaruaccelereringsfunktionen. Exekveringstiderna för olika kryptografiska algoritmer som behandlar data med olika storlekar samlas in och prestanda för varje kryptografisk algoritm utvärderas sedan.  Ett dataloggningsscenario utvärderas som en fallstudie där ESP32 regelbundet skickar data till en fjärrdatabas. Under olika konfigurationer av ESP32 jämförs överföringstiden för krypterad och icke-krypterad kommunikation via Hypertext Transfer Protocol Secure (HTTPS) och Hypertext Transfer Protocol (HTTP).  Resultaten kan användas för att förenkla beräkningen av prestanda / skydda avvägningar för specifika algoritmer. Det visar också att den inbyggda hårdvaruaccelerationen har en betydande inverkan på att öka dessa algoritmers prestanda. För Advanced Encryption Standard (AES) ökade genomströmningen för kryptering med 257,8% och för dekryptering 222,7%. För Secure Hash Algorithm (SHA-2) ökade kapaciteten med 165,2%. För Rivest-Shamir-Adleman (RSA) har krypteringsflödet minskat med 40,7% och dekryptering har ökat med 184%. Dessutom kan resultaten också hjälpa till att utforma och utveckla ett säkert IoT-system som innehåller enheter byggda med ESP32.

This dissertation thesis attends to problems of electronic registry for VUT. It deals with the principal of electronic registry functioning, electronic signature and it compares offer of the commercial registries. It goes in for the proposal and implementation of the electronic registry for VUT. Since the using of the e- registry on all public service Office was legalized the people can avoid long queues and the employees are avoided from the stress before dead lines. By the communication through the electronic registry is very important the electronical signature. It is almost a full-valued and lawful alternative to the physical signature. For its safety and utility this system employes asymmetric codes and hash algorithm. Presently in many states, where the electronical signature is legalized it is used together with standard X 509 which defines the format of certificates, organization and action of certification authorities. The certification autority ensures safe connection of the person and general key for using of the electronical signature.

Cao Yidan. / "Architecture Department, Chinese University of Hong Kong, Master of Architecture Programme 2008-2009, design report." / Includes bibliographical references (leaf 143). / Research phrase / Chapter Introduction --- Problem Define --- p.10 / Thesis Statement --- p.16 / Thesis Schedule --- p.18 / Chapter Methodology Study --- Introduction --- p.22 / Case Study --- p.24 / Summary --- p.48 / Chapter School Study --- Introduction --- p.52 / Time Line & Typology --- p.54 / Millenary School --- p.58 / Design phrase / Chapter Design Study --- Instroduction --- p.74 / Separation & Connection --- p.76 / Modularity --- p.78 / Standardized Component --- p.80 / Chapter Design Proposal --- Site --- p.86 / Architecture --- p.90 / Presentation Panel --- p.91 / Chapter Appendix --- Interpreation --- p.114 / Prefabrication Study --- p.122

It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.