We investigate the silicon (Si) cycle in the Southern Ocean through two isotopic approaches: (1) 30Si-incubation experiments and (2) natural silicon isotopic composition (ä30Si). 30Si-spiked incubation allows to discriminate the short-term (~ 1 day) net Si-uptake flux in bSiO2 production and dissolution. ä30Si of both biogenic silica and dissolved silicon integrates at seasonal/annual scale bSiO2 production or dissolution and mixing. (1) A new mass spectrometer method (HR-SF-ICPMS) has been developed for 30Si-isotopic abundance measurements. This methodology is faster and easier than the previous available methodologies and has the same precision. A complete set of incubation was coupled with parallel 32Si-incubations and the two methodologies give not significantly different bSiO2 production rates. In the Southern Ocean, especially in the southern Antarctic Circumpolar Current, the large silicic acid concentration degrades the sensitivity of the method with Si dissolution fluxes staying generally below the detection limit. In contrast, the 28Si-isotopic dilution was sensitive enough to assess low biogenic silica dissolution rates in silicic acid poor waters of the northern ACC. We show that large accumulation of detrital dissolving biogenic silica after productive period implies really efficient silicon loop with integrated (euphotic layer) dissolution:production ratio equal or larger than 1. (2) We largely expand the silicic acid isotopic data in the open ocean. Relatively simple mass and isotopic balances have been performed in the Antarctic Zone and have allowed to apply for the first time ä30Si in a quantitative way to estimate regional net silica production and quantify source waters fueling bSiO2 productivity. We observe that at the end of the productive period as suggested with 30Si-incubation, large accumulation of detrital biogenic silica in the surface waters increase the D:P ratio and subsequently dampens the bSiO2 production mediated isotopic fractionation with residual biogenic silica carrying heavier ä30Si than expected. Seasonal isotopic evolution is simulated and seems in agreement with our observations. These simulations strongly suggest working with non-zero order equations to fully assess the seasonal expression of the different processes involved: mixing, uptake, dissolution. Si-isotopes are also tracking the origin and fates of the different ACC pools across the Southern Ocean meridional circulation. Moreover during the circumpolar eastward pathway, the bSiO2 dissolution in deep water decreases the corresponding ä30Si values and this imprint is further transmitted via the upper limb of the meridional circulation in the intermediate water masses.

The main objective of the present work is the removal of inclusions from silicon scrap and metallurgical grade silicon. To reach this goal, two various routes are investigated. First, settling of SiC particles from molten silicon followed by directional solidification is reported in this thesis. Then, removal of SiC and Si3N4 inclusions in silicon scrap by filtration with foam filters and wettabilities of silicon on graphite materials are studied. To supply the increasing needs of the photovoltaic industry it is necessary to produce a low cost silicon feedstock. One of the many routes established from the industry is the Solsilc project. This project aims to produce solar-grade silicon by carbothermal reduction of silicon, based on the use of very pure raw materials. The high carbon content of about 700 mass ppm of the silicon in the form of SiC particles, needs to be removed before the Solsilc silicon could be used as a feedstock to PV industry. Settling of SiC particles in molten silicon was investigated. This part of the work was in cooperation with SINTEF Materials & Chemistry. Two experiments were conducted and the cast silicon ingots were analyzed by light microscopy and LECO carbon analyzer. The results showed that the number of inclusions in the middle of the ingots was less than in the bottom and top. The removal efficiency was above 96% in the middle part of an ingot and the total carbon content measured by LECO was < 25 mass ppm. The difference in density between the particles and the melt gives the SiC particles a relatively high settling velocity leading to a high removal efficiency. Pushing and engulfment of SiC particles by solidification front was also studied. Directional solidification of silicon that followed settling pushes the particles to the top of the ingot. The presence of SiC particles in the middle of the ingot is explained by engulfment. Top-cut silicon scrap represents a considerable loss of the PV silicon. Removal of inclusions from the silicon scrap would make it possible to recycle it to feedstock in the PV cell production. This was carried out by filtration with ceramic foam filters. Carbon and SiC foam filters with various pore sizes were employed in the filtration experiments. They were provided by Eger-Sørensen, a Norwegian company and Foseco AB in Sweden. The top-cut silicon scrap came from REC-Scan Wafer. Characterization of inclusions in silicon scrap before and after filtration experiments took place. Two techniques were developed and used in this work. First, extraction of inclusions by acid dissolution of the silicon was carried out. The SiC and Si3N4 particles collected afterwards were analyzed and counted by automated light microscopy. In the second technique, silicon samples were ground and polished with diamond paste. Microscopic analysis consisted of measuring the surface area of the inclusions found in the silicon samples. Results show that inclusions in top-cut solar cell silicon scrap are needle-like Si3N4 particles and round SiC inclusions. The removal efficiency for a 30 ppi SiC filter is more than 99%. The inclusions remaining after filtration are mainly SiC particles smaller than 10 µm. The experiments show that the filtration efficiency increases with decreasing filter pore size. Some filter cakes that mainly consist of large Si3N4 inclusions are found on the top surface of the filter. Deep bed filtration is the mechanism responsible for the removal of small particles. After taking into consideration various models for the foam filters the main conclusion is that interception seems to be the main removal mechanism of inclusions in silicon. Settling appears to play a minor role for our system. A new model named branch model explains better the experimental results. Due to the low wetting angle between molten metal and the filter material, capillary forces drive the melt through the filter. Therefore, the melt velocity through the filter is high. This justifies the usage of potential flow in the branch model.   It is shown that molten silicon may be contaminated in contact with the refractories. Since purity for solar cell silicon is crucial, contamination must be minimized. Graphite crucibles may be a source of relatively high levels of Al, Fe, and P. In the filtration process, wettability of the molten silicon with the filter material is very important. Thus, spreading and infiltration of molten silicon into the graphite substrates were also investigated in this thesis. Five different graphites were provided by Svenska Tanso AB. They are in use as refractories in the PV industry and vary from each other in porosity, density, and average pore size. The sessile drop technique is employed to study the wetting behavior of molten silicon on the graphite materials. The measured contact angles show that molten silicon does not initially wet carbon materials. However, due to the chemical reaction between Si and C, a SiC layer is formed in the interface between molten silicon and the graphite. Formation of this layer lowers the contact angles finally reaching equilibrium wetting angles of molten silicon with SiC materials. Spreading of molten silicon is affected not only by the reaction formed SiC layer, but also by the surface finish. The final contact angles, also called equilibrium contact angles, decrease with increasing surface roughness of the graphites. Infiltration of silicon into graphites is mainly related to the average pore size of graphite materials. Materials with large pores are penetrated deeper by the liquid silicon. Zero contact angles of the silicon with graphites are found in materials with both high surface roughness and large average pore size. These results indicate that graphites for use in the PV industry should have a small average pore size. The surface of the graphite in direct contact with silicon should be smooth (low roughness).

Semiconductor nanotechnology is today a very well studied subject, and demonstrations of possible applications and concepts are abundant. However, well-controlled mass-fabrication on the nanoscale is still a great challenge, and the lack of nanofabrication methods that provide the combination of required fabrication precision and high throughput, limits the large-scale use of nanodevices. This work aims in resolving some of the issues related to nanostructure fabrication, and deals with development of nanofabrication processes, the use of size-reduction for reaching true nanoscale dimensions (20 nm or below), and finally the optical and electrical characterization to understand the physics of the more successful structures and devices in this work. Due to its widespread use in microelectronics, silicon was the material of choice throughout this work. Initially, a fabrication process based on electron beam lithography (EBL) was designed, allowing controlled fabrication of devices of dimensions down to 30 nm, although, generally, initial device dimensions were above 70 nm, allowing the flexible but low-throughput EBL, to be replaced by state-of-the-art optical lithography in the case of industrialization of the process. A few main processes were developed throughout the course of this work, which were capable of defining silicon nanopillar and nano-wall arrays from bulk silicon, and silicon nanowire devices from silicon-on-insulator (SOI) material. Secondly, size-reduction, as a means of providing access to few-nanometer dimensions not available by current lithography techniques was investigated. An additional goal of the size-reduction studies was to find self-limiting mechanisms in the process, that would limit the impact of variations in the size and other imperfections of the initial structures. Thermal oxidation was investigated mainly for self-limited size-reduction of silicon nanopillars, resulting in well-defined quantum dot arrays of few-nm dimensions. Electrochemical etching was employed to size-reduce both silicon nanopillars and silicon nanowires down into the 10-nm regime. This being a novel application, a more thorough study of electrochemical etching of low-dimensional and thin-layer structures was performed as well as development of a micro-electrochemical cell, enabling electrochemical etching of fabricated nanowire devices with improved control. Finally, the combination of nanofabrication and size-reduction resulted in two successful device structures: Sparse and spatially well-controlled single silicon quantum dot arrays, and electrically connected size-reduced silicon nanowires. The quantum dot arrays were investigated through photoluminescence spectroscopy demonstrating for the first time atomic-like photoemission from single silicon quantum dots. The silicon nanowire devices were electrically characterized. The current transport through the device was determined to be through inversion layer electrons with surface states of the nanowire surfaces greatly affecting the conductance of the nanowire. A model was also proposed, capable of relating physical and electrical properties of the nanowires, as well as demonstrating the considerable influence of charged surface states on the nanowire conductance. / QC 20101101

Semiconductor technology has already got into nanometer scale. As the dimension keeping scale down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed. In order to get strain from the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress. By this way, we successfully improve drain current and mobility of NMOS into 12% and 6%, respectively. But there is no variation for PMOS. In addition, by DC stress, we can understand the hot carrier effect to strained silicon. In this work, both NMOS and PMOS present the same result, this is, as the silicon substrate is bent, the sharper of the curve, the worse of the reliability.

The usual way to remove the silicon layer is used by the solutions of HF and KOH to conduct the etching process, but those chemicals are dangerous for the humans. Therefore, this study proposes the method that uses the diamond millstone to reduce the thickness of the silicon wafer. It hopes that this method can effectively shorten the process time and reduce the amount of chemical pollution. Firstly, the effects of the working pressure, the rotating speed of the wafer, and the diamond millstone on the removing rate of silicon wafer are investigated. Then, the effect of the working pressure on the flatness of the wafer surface is investigated. Finally, the effect of the rotating speed ratio of the wafer to the diamond millstone on the track type of grinding surface is theoretically analyzed. According to the experimental results, the removing rate of silicon wafer is almost linearly proportional to the working pressure, the rotating speed of the wafer, and the diamond millstone. The lighter working pressure, the more flatness of the wafer is. According to the theoretical results, the rotating speed ratio of the wafer to the diamond millstone influences the track type of grinding surface. When this rotating speed ratio is an irrational number, the distribution of grinding track becomes finer.

This thesis is to research connection process of multi-level conductor in integration circuits (ICs) manufacture technology. For the sake of sub-micro ICs which is gazed by people in the future, device¡¦s dimension have to be scaled down unceasingly; besides, the design of conductor connection of multi-level metal is also to be adopted for ULSI technology. However, the number of metal connection layer is increasing as well as the distance between wires is shorter and shorter, which leads to the fact that the RC delay time of metal interconnection is the primary reason of limiting the speed of semiconductor device while electronic signal is delivered among metal interconnection. In order to lower delay time of signal propagation, there are two parts in the following: In the aspect of lowering resistance, we substitute copper (resistance is 1.7£g£[-cm) at present for aluminum (resistance is 2.7£g£[-cm ) in the past so as to make copper be the wire for interconnection system. Furthermore, the scaled down device not only increase the current density of the wire but also increase the severity of electromigration inside the wire. Copper atoms are so heavier than aluminum atoms that copper atoms can restrain electromigration appropriately. In the aspect of decreasing capacitance, we will develop low dielectric constant (low-k). But copper with Damascene manufacture under the conditions of external operation such as temperature and electric field give rise to the fact that Cu diffuses into low-k material so easily that copper and low-k interact, which deteriorates the characteristic of the material¡Braises the leakage current and leads to the breakdown of the dielectric material. Therefore, it must be an important topic for study that we search for the dielectric barrier material with the characteristic against copper diffusion under the demand coinciding with integration process compatibility. At present, because of the material film called silicon carbide with low dielectric constant (k=4~6) attracts a lot of people¡¦s eyes deeply, it can applied to dielectric barrier technology to replace traditional dielectric barrier silicon nitride with high dielectric constant (k~8) for the purpose of alleviating delay time of the wire system. This thesis will discuss fundamental characteristics of silicon carbide film and some problems during the integration process. For instance, the impacts on silicon carbide under the conditions of fluorine plasma and thermal treatment; furthermore, this thesis will research the electric problems from the integration of low-k dielectric barrier and copper wire as well as probes into mechanism of leakage current.

Recent technological advances have allowed silicon (Si) semiconductor technology to approach the theoretical limits of the Si material; however, power device requirements for many applications are at a stage that the present Si-based power devices cannot handle. The requirements include higher blocking voltages, switching frequencies, efficiency, and reliability. Material technologies superior to Si are needed for future power device developments. Silicon Carbide (SiC) based semiconductor devices offer one such alternative. SiC based power devices exhibit superior properties such as very low switching losses, fast switching behavior, improved reliability and high temperature operation capabilities. Power factor correction stage of power supplies is identified as an area where application of these devices would prove advantageous. In this thesis a high performance, high efficiency, SiC based power factor correction stage is discussed. The proposed topology takes advantage of the superior properties of SiC semiconductor based devices and the reduced number of devices that the dual boost power factor correction topology requires to achieve high efficiency, small size and better performance at high temperature. In addition to this analysis of SiC based power devices is carried out to study their characteristics and performance.

The thesis provides the required knowledge base for establishing Laser Induced Stress Wave Thermometry (LISWT) as a viable alternative to current infrared technologies for temperature measurement up to 1000°C with ±1°C resolution. The need for a non-contact, high resolution thermal measurement methodology applicable to Rapid Thermal Processing (RTP) motivated the work. A stress wave propagation model was developed and a complex, temperature-dependent elasto-viscoplastic constitutive law was identified. A stagger-grid finite difference scheme was followed to approximate the solution field subject to temperature and plate thickness variations. Extensive numerical experiments were conducted to identify the proper time and spatial steps. A Gabor wavelet transform scheme was also employed for the extraction of wafer thermal and geometric information from exploring wave attenuation and dispersion. Researched results concluded that wave group velocity is a nonlinear function of temperature. Nonlinearity became more prominent at high temperatures and low frequencies. As such, for LISWT to achieve better thermal resolution at high temperatures, low frequency components of the induced stress wave should be exploited. The results also showed that the influence of temperature on attenuation is relatively small. It is not recommended to use attenuation for resolving temperature variation as small as several degrees Celsius. In addition to temperature, geometry also was found to have an impact on wave dispersion and attenuation. The results showed that the influence of thickness on wave velocity is significant, thus suggesting that for LISWT to achieve high temperature resolution, wafer thickness must be accurately calibrated in order to eliminate all possible errors introduced by thickness variation. The study established the basic framework for LISWT to be applicable to silicon wafer RTP at elevated temperatures. The model and methods developed for the course of the research can be easily adapted to account for other nondestructive evaluation applications involving the use of surface, plate or bulk waves for material characterization and thermal profiling.

In this study, a particle welding tester has been employed to weld the 500 £gm diamond particle coated copper on the aluminum workpiece surface. The DC power supply is used as the welding energy to weld. The resistance material is added into the interface between the electrode and the diamond particle. Hence the welding energy can transfer from the diamond particle to aluminum surface so that the aluminum softens and the diamond particle is embedded into the surface under the applied force. In this experiment, the effects of the applied force (2-20 N), power (13-35 W) on the welding pattern and the behavior of welding interface. When the silicon carbide is used as the resistance material, the weld able region map is established in terms of the applied force and power. The map is divided into the insufficient heat input, the normal welding and the excess heat input. In the insufficient heat input region the power is less than 20 W, and the diamond can not be embed into the workpiece surface because the power is not enough. In the normal welding region, the power is in the range between 20 to 30 W, where the welding quality is quite good. In the excess heat input region, the power is greater than 30 W, where the welding quality is poor because the blowhole and the gas hole are generated on the surface. In the normal welding region, the embedded depth can be controlled by the different force during welding process.

Thesis (M.S.E.C.E.)--University of Delaware, 2009. / Principal faculty advisors: Ian Appelbaum and James Kolodzey, Dept. of Electrical & Computer Engineering. Includes bibliographical references.