The objective of the research in this thesis was to develop high-efficiency n-type silicon solar cells at low-cost to reach grid parity. This was accomplished by reducing the electrical and optical losses in solar cells through understanding of fundamental physics and loss mechanisms, development of process technologies, cell design, and modeling. All these technology enhancements provided a 3.44% absolute increase in efficiency over the 17.4% efficient n-type PERT solar cell. Finally, 20.84% efficient n-type PERT (passivated emitter and rear totally diffused) solar cells were achieved on commercial grade 239cm2 n-type Cz silicon wafers with optimized front boron emitter without boron-rich layer and phosphorus back surface field, silicon dioxide/silicon nitride stack for surface passivation, optimized front grid pattern with screen printed 5 busbars and 100 gridlines, and improved rear contact with laser opening and physical vapor deposition aluminum. This thesis also suggested research directions to improve cell efficiency further and attain ≥21% efficient n-type solar cells which involves three additional technology developments including the use of floating busbars, selective emitters, and negatively charged aluminum oxide (Al2O3) film for boron emitter surface passivation.

Graphene has been one of the most interesting and widely investigated materials in the past decade. Because of its high mobility, high current density, inherent strength, high temperature stability and other properties, scientists consider it a promising material candidate for the future all-carbon electronics. However, graphene still exhibits a number of problems such as an unknown interface structure and no sizable band gap. Therefore, the purpose of this thesis is to probe and solve these problems to make graphene suitable for electronics. The work focuses on high-quality C-face epitaxial graphene, which is grown on the (000-1) face (C-face) of hexagonal silicon carbide using the confinement-controlled sublimation method. C-face epitaxial graphene has much higher mobility compared to Si-face graphene, resulting from its special stacking order and interface structure, the latter of which is not fully understood. Thus, the first part of the work consists of a project, which is to investigate and modify the interface and the surface of C-face graphene by silicon deposition and annealing. Results of this project show that silicon can intercalate into the graphene-SiC interface and form SiC by bonding carbon atoms on the graphene surface. Another crucial problem of graphene is the absence of a band gap, which prevents graphene from becoming an ideal candidate for traditional digital logic devices. Therefore, the second project of this work is devoted to introducing a wide band gap into the graphene electronic structure by growing from a nitrogen-seeded SiC. After successful opening of a band gap, a pre-patterning method is applied to improve graphene thickness variations, orientational epitaxy, and the gapped electronic structure.

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published_or_final_version / abstract / toc / Physics / Master / Master of Philosophy

published_or_final_version / abstract / toc / Physics / Master / Master of Philosophy

published_or_final_version / abstract / toc / Physics / Doctoral / Doctor of Philosophy