Colloidally synthesized silicon (Si) and germanium (Ge) were explored as high capacity anode materials in lithium ion batteries. a-Si:H particles were synthesized through the thermal decomposition of trisilane in supercritical n-hexane. Precise control over particle size and hydrogen content was demonstrated. Particles ranged in size from 240-1500 nm with hydrogen contents from 10-60 atomic%. Particles with low hydrogen content had some degree of local ordering and were easily crystallized during Raman spectroscopy. The as-synthesized particles did not perform well as an anode material due to low conductivity. Increasing surface conductivity led to enhanced lithiation potential. Cu nanoparticles were deposited on the surface of the a-Si:H particles through a hydrogen facilitated reduction of Cu salts. The resulting Cu coated particles had a lithiation capacity seven times that of pristine a-Si:H particles. Monophenylsilane (MPS) grown Si nanowire paper was annealed under forming gas to reduce a polyphenylsilane shell into conductive carbon. The resulting paper required no binder or carbon additive and achieved capacities of 804 mA h/g vs 8 mA h/g for unannealed wires. Si and Ge heterostructures were explored to take advantage of the higher inherent conductivity of Ge. Ge nanowires were successfully coated with a-Si by thermal decomposition of trisilane on their surface, forming Ge@a-Si core shell structures. The capacity increased with increasing Si loading. The peak lithiation capacity was 1850 mA h/g after 20 cycles – higher than the theoretical capacity of pure Ge. MPS additives created a thin amorphous shell on the wire surfaces. By incubating the wires after MPS addition the shell was partially reduced, conductivity increased, and a 75% increase in lithiation capacity was observed for the nanowire paper. The syntheses of Bi and Au nanoparticles were also explored. Highly monodisperse Bi nanocrystals were produced with size control from 6-18 nm. The Bi was utilized as seeds for the SLS synthesis of Ge nanorods and copper indium diselenide (CuInSe2) nanowires. Sub 2 nm Au nanocrystals were synthesized. A SQUID magnetometer probed their magnetic behavior. Though bulk Au is diamagnetic, the Au particles were paramagnetic. Magnetic susceptibility increased with decreasing particle diameter. / text

Pre-silicon verification is an essential part of integrated circuit design to capture functional design errors. Complex simulation, emulation and formal verification tools are used in a virtual environment before the device is manufactured in silicon. However, as the design complexity increases and the design cycle becomes shorter for fast time-to-market, design errors are more likely to escape from the pre-silicon verification and functional bugs are found during the actual operation. Since manufacturing test primarily focuses on the physical defects, post-silicon validation is the final gatekeeper to capture these escaped design bugs. Consequently, post-silicon validation has become a critical path in shortening the development cycle of System-On-Chip(SoC) design. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for silicon debugging. Since a post-silicon validation operates on a fabricated chip, recording the values of each and every internal signals is not possible. Due to this limitation of post-silicon validation, acquiring the circuit's internal behavior with the limited available resources is a very challenging task in post-silicon validation. There are two main categories to expand the observability: trace and scan signal based approaches. Real time system response during silicon debug can be acquired using a trace signal based technique; however due to the limited space for the trace buffer, the selection of the trace signals is very critical in maximizing the observability of the internal states. The scan based approach provides high observability and requires no additional design overhead; however the designers cannot acquire the real time system response since the circuit operation has to be stopped to transfer the internal states. Recent research has shown that observability can be enhanced if trace and scan signals can be efficiently combined together, compared to the other debugging scenarios where only trace signals are monitored. This dissertation proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals using restorability values to maximize the observability of internal circuit states. In order to achieve this goal, we first introduce a technique to calculate restorability values accurately by considering both local and global connectivity of the circuit. Based on these restorability values, the dynamic trace signal selection algorithm is proposed to provide a higher number of restored states regardless of the incoming test vectors. Instead of using total restorability values, we separate 0 and 1 restorability values to differentiate the different circuit responses to the different incoming test vectors. Also, the two groups of trace signals can be selected dynamically based on the characteristics of the incoming test vectors to minimize the performance degradation with respect to the different incoming test vectors. Second, we propose a new algorithm to find the optimal number of trace signals, when trace and scan signals are combined together for better observability. Our technique utilizes restorability values and finds the optimal number of trace signals so that the remaining space of trace buffer can be utilized for the scan signals. Observability can be enhanced further with data compression technique. Since the entries of the dictionary are determined from the golden simulation, a high compression ratio can be achieved with little extra hardware overhead. Experimental results on benchmark circuits and a real industry design show that the proposed technique provides a higher number of restored states compared to the existing techniques. / text

Timing analysis is a key sign-off step in the design of today's chips, but technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models ranging from the basic MOSFET device model to full-chip models of important performance metrics including power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability and the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this research is (i) to introduce special-purpose test structures that specifically focus on ensuring the accuracy of gate timing models, and (ii) to introduce methods that analyze the extracted information, in the form of path delay measurements, using the proposed test structures. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing Static Timing Analysis (STA), which, in turn, is based entirely on the gate timing models. The proposed test structures compare favorably to alternative approaches; they are far easier to measure than direct delay measurement, and they are much more general than simple ring-oscillator structures. Furthermore, the structures are specified at a high level, allowing them to be synthesized using a standard ASIC place-and-route flow, thus capturing the local layout systematic effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. For the silicon timing analysis, we propose methods that deduce segment delays from the path delay measurements. These estimated segment delays using our methods can be directly compared with the timing models. Therefore, it will be easy to identify the cause of timing mismatches. Deducing segment delays from path delays, however, is not an easy problem. The difficulties associated with deconvolving segment delays from measured path delays come from insufficient sampling points. To overcome this limitation, we first group the segments based on certain characteristics of segments, and adapt Moore-Penrose pseudo-inverse method to approximately solve the segment delays. Secondly, we used equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. We also propose another improved test structure that has a built-in test pattern generator, and hence does not require ATPG (Automatic Test Pattern Generation). It is a self-timed circuit, and this feature makes the test structure run as fast as it can. Therefore, measurements can be made under high speed switching conditions. Finally, we can study dynamic effects such as timing effects of different levels of switching activities and voltage drop with the new test structure. / text

published_or_final_version / Physics / Master / Master of Philosophy

published_or_final_version / Physics / Master / Master of Philosophy

Silicon has been the material of choice of the photonics industry over the last decade due to its easy integration with silicon electronics as well as its optical transparency in the near-infrared telecom wavelengths. Besides these, it has very high refractive index, and also a broad optical transparency window over the entire mid-IR till about 8[Mu]m. Photonic crystal is well known that it can slow down the speed of light. It also can provide a universal platform for microcavity optical resonators with high quality factor Q and small modal volumes. The slow light effect, high Q and small modal volumes enhance light-matter interaction, together with high refractive index of silicon can be utilized to build a highly sensitive, high throughput sensor with small footprint. In this research, we have demonstrated highly compact and sensitive silicon based photonic crystal biosensor by engineering the photonic crystal microcavity in both cavity size and cavity-waveguide coupling condition. We have developed solutions to increase biosensor throughput by integrating multimode interference device and improving the coupling efficiency to a slow light photonic crystal waveguides. We have also performed detailed investigations on silicon based photonic devices at mid-infrared region to develop an ideal platform for highly sensitive optical absorption spectroscopy on chip. The studies have led to the demonstration of the first slot waveguide, the first photonic crystal waveguide, and the first holey photonic crystal waveguide and first slotted photonic crystal waveguide in silicon-on-sapphire at mid-infrared. The solutions and devices we developed in our research could be very useful for people to realize an integrated photonic circuit for biological and chemical sensing in the future. / text

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Using a novel two-beam technique developed to greatly enhance quadrupolar contributions to the second-order nonlinear polarization, we performed a nonlinear spectroscopic study of silicon nanocrystals implanted in an SiO₂ matrix.