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In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we divide the thesis into two parts, strained-silicon channel engineering and high-k/metal gate stacks respectively. Firstly, to study the influence of stress on carrier transport properties, we proposed an approach to get uniaxial compressive/tensile stress from the channel by bending silicon substrate to enhance device performance. By applying uniaxial longitudinal tensile/compressive stress, the drain current and mobility were found to increase obviously in n/p-type MOSFETs, respectively. The enhancement can be attributed to the reduction of effective transport mass and to the suppression of inter-valley scattering. However, we found that the external mechanical stress aggravated hot carrier effects in n-type MOSFETs. Therefore, in n-type MOSFETs, the behaviors of the substrate current and the impact ionization rate under mechanical stress are investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current has significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the band gap. In p-type MOSFETs, the reliability issue, named negative bias temperature instability, is the dominant degradation mechanism during ON-state operation. Therefore, we investigate the NBTI characteristics of strained p-type MOSFETs with external uniaxial tensile/compressive stress. The results indicate that uniaxial compressive stress not only enhances drive current but also reduces NBTI degradation. On the contrary, uniaxial tensile stress leads to a significant degradation in both of drive current and NBTI behavior. The observed Cgc-Vg curve shows the inversion capacitance is strongly dependent on mechanical strain, meaning that the probability of electrochemical reaction decreases/or increases due to the changes in inversion carrier density according to the Nit generation rate of the reaction-diffusion model. Moreover, the charge pumping result is also consistent with the threshold voltage shift of the strained device, which means the degradation is mainly due to trap generation at the Si/SiO2 interface. In addition, to investigate the influences of biaxial compressive stress on p-MOSFETs, we attempts to combine intrinsic and external mechanical stress. It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised Source/Drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature. However, this phenomenon was inverted above 363K. Because hole can gain enough thermal energy to transit to higher energy level by inter-valley scattering, its transport mechanism was dominated by lower effective mass at higher energy level. Besides, the model is also evidenced that the mobility degradation under biaxial compressive stress becomes aggravated while temperature decreases from 300 K to 100 K, which is mainly due to the increase of the ratio of carriers occupied in lowest band. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 65 nm technology node due to unacceptable gate leakage current. Therefore, in the second section of this thesis, we established the electrical characteristics and physical mechanisms of MOSFETs with HfO2 dielectric/TiN gate by analyzing experimental data from charge pumping, split C-V, DC Id-Vg, and pulse Id-Vg. It is found that the threshold voltage (Vth) has a significant decrease as titanium increases in metal gate for n-MOSFETs, whereas the Vth increases in p-MOSFETs. By examining flat band voltage, we found the Vth shift was resulted from metal gate work function (£pm) which became smaller as titanium increased in metal gate. In addition,the dependence of effective mobility on temperature from 100K to 300K was entirely analyzed, which indicated HfO2 remote phonon scattering as the dominant cause of the mobility degradation in n- and p-type MOSFETs when titanium decreased. However, the gate leakage current is also strongly dependent on the nitrogen in metal gate. It is proved that the nitrogen can assivate the traps in HfO2 by pulse I-V,leading to the decrease in gate leakage dominated by Frenkel- Poole mechanism.

For the high performance integrated circuits applications such as microprocessors, memories and high power devices, the metal-oxide-semiconductor field effect transistors (MOSFETs) is the most important device due to its low cost, power consumption and scalable property especially. However, the aggressive scaling of conventional MOS devices suffered from noticeable short channel effects such as drain induction barrier lower, punch through, and direct tunneling gate leakage. Those problems not only lower the gate control ability but also increase the standby power consumption. For future VLSI devises below 65 nm regimes, silicon-on-insulator (SOI) and high-k/metal gate MOSFETs are considered to be possible candidates because of faster operation speed and lower power consumption. Therefore, this dissertation investigates the electrical characteristics and reliability issues of novel MOSFETs for 65 nm and below technology. It is roughly divided into two parts, partially depleted (PD) SOI MOSFETs and high-k/metal gate stack MOSFETs, respectively. In the first part, we systematically investigate the mechanism of gate-induced floating body effect (GIFBE) for advanced PD SOI n-MOSFETs. Based on different operation conditions, it was found that the dominant mechanism can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron-valence band (EVB) tunneling. Analyzing the GIFBE in different temperature provides further evidence that the accumulation of holes in the body results from the AHI induced direct tunneling current from the poly-Si gate. In addition, we proposed an approach by bending silicon substrate to further study the impact of mechanical strain on GIFBE. The experimental result indicates that the strain effect indeed decreases the gate leakage current, but increases the hole-valence band (HVB) tunneling current, which indicates that GIFBE becomes serious under mechanical strain. Based on our proposed AHI model, this phenomenon can be mainly due to strain-induced band gap narrowing in the poly-Si gate. In p-type MOSFETs, the reliability issue, named negative bias temperature instability (NBTI), is the dominant degradation mechanism during ON-state operation. Therefore, we also investigate the GIFBE on NBTI degradation for PD SOI p-MOSFETs. The experimental results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ poly gate. However, based on different operation conditions, we found the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. Therefore, we propose the anode electron injection (AEI) model, similar to anode hole injection model, to explain how this main electron origin is generated during the NBTI stress. Finally, based on our proposed model, we further study influence of mechanical strain on GIFBE for SOI p-MOSFETs. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 45 nm technology node due to unacceptable gate leakage current. Therefore, in the second part of this thesis, we investigate the electrical characteristics and physical mechanisms for MOSFETs with HfO2/TixN1-x stacks by using split C-V, DC Id-Vg, and charge pumping techniques. The experimental results indicates that different ratio of Ti strongly affect various parameters, including threshold voltage, mobility, and subthreshold swing, respectively. In addition, the gate leakage current is also strongly dependent on the nitrogen in metal gate. By charge pumping technique, it was found that with increasing Ti concentration of metal gate, there is a trade-off relationship among the interface traps and bulk defects of high-k dielectric. This phenomenon is associated with the amount of nitride diffusion from the metal gate to high-k bulk and SiO2/Si interface layer. In the aspects of reliability, charge trapping in high-k gate stacks remains an important issue since it causes the threshold voltage (Vth) shift and drive current degradation. This phenomenon can be attributed to a large number of pre-existing traps in the high-k dielectric layer. In real circuit operation, the devices are generally operated in the dynamic condition. Therefore, the following study further investigates Vth instability of Hf-based n-MOSFETs under the dynamic bias operation. The static condition was also performed on the identical device for a comparison. The results indicate threshold voltage (Vth) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. In addition, the Vth shift clearly increases with an increase in dynamic stress operation frequency. According to these experimental results, we propose a possible physical model for electron trapping phenomena under dynamic stress. Based on our proposed model, we further dynamic stress induced charge trapping characteristics for devices with different Ti1-xNx composition of metal-gate electrodes. In addition, we further respectively investigates the temperature dependence of dynamic positive bias stress (PBS) and negative bias stress (NBS) degradation in n-type and p-type MOSFETs with high-k/metal gate stacks. The experimental results indicate there is a contrary trend in temperature dependence of Vth shifts for n- and p-MOSFETs under dynamic PBS and NBS, respectively. The Vth shift decreases with increasing temperature for n-MOSFETs under dynamic PBS. This is due to the thermal emission of trapped electrons in high temperature, leading to the reduction in. A contrary trend with temperature for p-MOSFETs under dynamic NBS can be attributed to the interface trap generation induced by NBTI. On the other hand, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability concern in device scaling. However, the stress-induced drain leakage current degradation in device with high-k/metal gate stacks has not received as much attention. In fact, the GIDL behavior is associated with phenomenon of charge trapping in high-k dielectric layer. Therefore, the final study is to investigate the effects of channel hot carrier stress (CHCS) on the gate-induced drain leakage current (GIDL) for n-MOSFETs with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the IGIDL after CHCS, and observed that the magnitude of IGIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric.

The target of this thesis is to fabricate through Silicon via (TSV) structures based on Si-bench technology for high-speed transmission interface. In this process, Si via with a depth of 250 £gm were formed by dry etching on a 500 £gm thick <111> Si wafer. The TSV were then obtained by removing the bottom of the silicon wafer using grinding technique. To reduce microwave loss of high frequency signal transmission, we oxidized the TSV by oxygen wet oxidation at a temperature of 1000 oC. Finally, conductive paths through the TSV were formed by filling silver epoxy into the via and dry at a temperature of 200 oC for 1 hour. The s parameters of the high speed TSV structure was characterized by a Vector Network Analyzer. Si-bench technology can effectively improve system integration and performance while reducing cost and size of the module package. . Key words: Through silicon via, microwave loss, s parameters

Nanoscale science and technology demand novel approaches and new knowledge to further advance. Nanoscale fabrication has been widely employed in both modern science and engineering. Micro/nano lithography is the most common technique to deposit nanostructures. Fundamental research is also being conducted to investigate structural, physical and chemical properties of the nanostructures. This research contributes fundamental understanding in surface science through development of a new methodology. Doing so, experimental approaches combined with energy analysis were carried out. A delicate hardware system was designed and constructed to realize the nanometer scale lithography. We developed a complete process, namely laser-assisted scanning probe alloying nanolithography (LASPAN), to fabricate well-defined nanostructures in gold-silicon (Au-Si) system. As a result, four aspects of nanostructures were made through different experimental trials. A non-equilibrium phase (AuSi3) was discovered, along with a non-equilibrium phase diagram. Energy dissipation and mechanism of nanocrystalization in the process have been extensively discussed. The mechanical energy input and laser radiation induced thermal energy input were estimated. An energy model was derived to represent the whole process of LASPAN.

Copper has become the metal of choice for metallization, owing to its high electrical and thermal conductivity, relatively higher melting temperature and correspondingly lower rate of diffusivity. Most of the current studies can get high strength copper thin films but on an expense of conductivity. This study proposes a technique to deposit high strength and high conductivity copper thin films on different silicon substrates at room temperature. Single crystal Cu (100) and Cu (111) have been grown on Si (100) and Si (110) substrates, respectively. Single crystal Cu (111) films have a high density of growth twins, oriented parallel to the substrate surface due to low twin boundary energy and a high deposition rate. The yield strengths of these twinned Cu films are much higher than that of bulk copper, with an electrical resistivity value close to that of bulk copper. X-ray diffraction, transmission electron microscopy and nanoindentation techniques were used to show that high density twins are sole reason for the increase in hardness of these thin films. The formation of growth twins and their roles in enhancing the mechanical strength of Cu films while maintaining low resistivity are discussed.

The area of advanced gate dielectrics has gained considerable attention recently because semiconductor technology roadmaps predict for less than 2 nm equivalent oxide thickness (EOT) for next 10 years, and there are significant leakage current and reliability concerns for oxy-nitride in this regime. So it¡¦s an important business to use alternate high-k dielectrics instead of oxy-nitride. Titanium silicon oxide shows a low leakage current with a high dielectric constant for dielectric applications. Besides, barium doping can create additional oxygen vacancies that can enhance dielectric constant. In this study, we prepared barium doped titanium silicon by liquid phase deposition which is a novel material considered to have intermediate properties of silicon dioxide and titanium dioxide. From several characteristic measurements, we found that barium doped titanium silicon oxide with exhibiting higher dielectric constant, low leakage current and well interface state which is very promising candidates to instead of titanium silicon oxide. The physical and chemical properties of barium doped titanium silicon oxide films by means of several measuring instruments, including Fourier transform infrared spectrometer (FTIR), secondary ion spectrometer (SIMS), and X-Ray diffractometer (XRD). An Al / Ba doped titanium silicon oxide / Si metal-oxide-semiconductor (MOS) capacitor structure was used for the electrical measurements. The static dielectric constant of the O2-annealed barium doped titanium silicon oxide film can reach about 22.3. In addition, it has well leakage current density of 2.6 ¡Ñ 10-6 A/cm2 at 5 MV/cm with the equivalent oxide thickness 1.27 nm (optical thickness of 7.3 nm). It has high potential for dielectric applications.

In this thesis, high density plasma chemical vapor deposition (HDPCVD) is used to fabricate novel multiple quantum well structure of light emitting diodes (LEDs) and charge storaged layers of SONOS nonvolatile semiconductor memories (NVSMs). On the study of the light emitting diodes (LEDs) technology, wide band gap hydrogenated amorphous silicon carbide and porous silicon carbide has blue or green luminescence are currently being investigated for applications in optoelectronic devices. However, due to the indirect band gap character, the quantum efficiency of these LEDs is very low. In our experiment, we fabricate 5-periods hydrogenated amorphous silicon carbide multiple quantum well structure to enhance the luminescence efficiency. In our study, there are some following notable features: (1) The a-SixC1-x multiple quantum well structure prepared by high density plasma chemical vapor deposition and it shows visible photoluminescence at room temperature. (2) After fluorine ions implantation and thermal annealing, The PL energy of a-SixC1-x multiple quantum well shift to high energy. (3) The PL intensity of SiO2-barrier SixC1-x multiple quantum well is larger than SiNx-barrier. (4) The film adheres well to glass or Si wafer even at low deposition temperature, e.g. 200 0C by high density plasma chemical vapor deposition. On the study of the silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) technology, the SONOS is a multi-dielectric device consisting of an oxide-nitride-oxide (ONO) sandwich in which charge storage takes place in discrete traps in the silicon nitride layer. In addition to silicon nitride as the storage layer, we have studied the oxide/SiC:O/oxide sandwiched structures and thermal oxidation of SiC layer as a storage layer by HDPCVD processes. In our study, there are some following notable features: (1) From the capacitance-voltage and current-voltage characteristics of oxygen-incorporated silicon carbide with different oxygen content, it is observed that the memory window is decreased with increasing the oxygen content. By controlling the oxygen content, a higher breakdown voltage can be achieved. (2) In the study of the oxidation of SiC, it is found that low temperature (800 ¢J) oxidized SiC shows a larger memory window than that of the high temperature (925 ¢J) oxidized SiC by high density plasma chemical vapor deposition.

This study employed a commercial code FLUENT to simulate a chemical vapor deposition process in a rectangular chamber for deposition of a silicon dioxide layer on a rectangular substrate. We focus on the deposition rate and heat transfer coefficient (Nu number) on the substrate surface. We discuss the effects of the size of inlet region, the distance from inlet to substrate, the size of outlet region, the Reynolds number, the temperature of substrate, the ratio of the inlet flow rates of the two reaction gases on the deposition rate. The results show that the four corners at the substrate has the lowest deposition rate no matter how the variables are changed. Near the four corners there exist a region with high deposition rate. The deposition rate is more uniform when inlet is larger or equal to the substrate, and when the distance between the inlet and the substrate is small. The larger the size of the outlet region, the larger the uniform deposition rate region present on the central part of the substrate. The deposition rate increases with increasing Re number. However the uniformity remains similarly. The deposition rate also increases with increasing the substrate temperature. A study of the inlet flow rate ratio of TEOS and indicates that TEOS flow rate governs the process. A proper flow rate ratio gives a better deposition rate.

This study employed a commercial code to simulate a chemical vapor deposition process in a rectangular chamber for deposition of a silicon dioxide layer on a rectangular substrate. We focus on the deposition rate on the substrate surface. We discuss the effects of the Reynolds number, the distance from inlet to substrate, the size of inlet region, the temperature of the inlet region, and the temperature of substrate. The results show that as the temperature increase, the deposition rate on the substrate grows highly. This effect will decrease if the temperature is above the specific range. Besides, it is easily deposited unequally on the edge and corner region of the substrate. However, the central region on the substrate is still uniform. We could get bigger uniform area to adjust the proper conditions.