Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: James Kolodzey, Electrical and Computer Engineering. Includes bibliographical references.

Thesis (M.E.E.)--University of Delaware, 2006. / Principal faculty advisor: James Kolodzey, Electrical and Computer Engineering. Includes bibliographical references.

Thesis (Ph. D.)--University of Hong Kong, 2006. / Title proper from title frame. Also available in printed format.

Copper has become the metal of choice for metallization, owing to its high electrical and thermal conductivity, relatively higher melting temperature and correspondingly lower rate of diffusivity. Most of the current studies can get high strength copper thin films but on an expense of conductivity. This study proposes a technique to deposit high strength and high conductivity copper thin films on different silicon substrates at room temperature. Single crystal Cu (100) and Cu (111) have been grown on Si (100) and Si (110) substrates, respectively. Single crystal Cu (111) films have a high density of growth twins, oriented parallel to the substrate surface due to low twin boundary energy and a high deposition rate. The yield strengths of these twinned Cu films are much higher than that of bulk copper, with an electrical resistivity value close to that of bulk copper. X-ray diffraction, transmission electron microscopy and nanoindentation techniques were used to show that high density twins are sole reason for the increase in hardness of these thin films. The formation of growth twins and their roles in enhancing the mechanical strength of Cu films while maintaining low resistivity are discussed.

Nanoscale science and technology demand novel approaches and new knowledge to further advance. Nanoscale fabrication has been widely employed in both modern science and engineering. Micro/nano lithography is the most common technique to deposit nanostructures. Fundamental research is also being conducted to investigate structural, physical and chemical properties of the nanostructures. This research contributes fundamental understanding in surface science through development of a new methodology. Doing so, experimental approaches combined with energy analysis were carried out. A delicate hardware system was designed and constructed to realize the nanometer scale lithography. We developed a complete process, namely laser-assisted scanning probe alloying nanolithography (LASPAN), to fabricate well-defined nanostructures in gold-silicon (Au-Si) system. As a result, four aspects of nanostructures were made through different experimental trials. A non-equilibrium phase (AuSi3) was discovered, along with a non-equilibrium phase diagram. Energy dissipation and mechanism of nanocrystalization in the process have been extensively discussed. The mechanical energy input and laser radiation induced thermal energy input were estimated. An energy model was derived to represent the whole process of LASPAN.

Methylene-butyrolactones are readily accessed by two methodologies based on a particular ene reaction. Both methodologies have been applied to the synthesis of the northern fragment of Polycavernoside. A reverse Julia reaction was used as the key step of a new methodology towards triene frameworks ; a mechanistic study revealed the unexpected role of triflic acid in the field of metal triflates catalysed acylation of alcohols, and a new tandem Brook rearrangement-allylation sequence was developed in the viewpoint of an improved total synthesis of Polycavernoside A.

Silicon as a mono-crystalline bulk semiconductor is today the predominant material in many integrated electronic and photovoltaic applications. This has not been the case in lighting technology, since due to its indirect bandgap nature bulk silicon is an inherently poor light emitter.With the discovery of efficient light emission from silicon nanostructures, great new interest arose and research in this area increased dramatically.However, despite more than two decades of research on silicon nanocrystals and nanowires, not all aspects of their light emission mechanisms and optical properties are well understood, yet.There is great potential for a range of applications, such as light conversion (phosphor substitute), emission (LEDs) and harvesting (solar cells), but for efficient implementation the underlying mechanisms have to be unveiled and understood.Investigation of single quantum emitters enable proper understanding and modeling of the nature and correlation of different optical, electrical and geometric properties.In large numbers, such sets of experiments ensure statistical significance. These two objectives can best be met when a large number of luminescing nanostructures are placed in a pattern that can easily be navigated with different measurement methods.This thesis presents a method for the (optional) simultaneous fabrication of luminescent zero- and one-dimensional silicon nanostructuresand deals with their structural and optical characterization.Nanometer-sized silicon walls are defined by electron beam lithography and plasma etching. Subsequent oxidation in the self-limiting regime reduces the size of the silicon core unevenly and passivates it with a thermal oxide layer.Depending on the oxidation time, nanowires, quantum dots or a mixture of both types of structures can be created.While electron microscopy yields structural information, different photoluminescence measurements, such as time-integrated and time-resolved imaging, spectral imaging, lifetime measurements and absorption and emission polarization measurements, are used to gain knowledge about optical properties and light emission mechanisms in single silicon nanocrystals.The fabrication method used in this thesis yields a large number of spatially separated luminescing quantum dots randomly distributed along a line, or a slightly smaller number that can be placed at well-defined coordinates. Single dot measurements can be performed even with an optical microscope and the pattern, in which the nanostructures are arranged, enables the experimenter to easily find the same individual dot in different measurements.Spectral measurements on the single dot level reveal information about processes that are involved in the photoluminescence of silicon nanoparticles and yield proof for the atomic-like quantized nature of energy levels in the conduction and valence band, as evidenced by narrow luminescence lines (~500 µeV) at low temperature. Analysis of the blinking sheds light on the charging mechanisms of oxide-capped Si-QDs and, by exposing exponential on- and off-time distributions instead of the frequently observed power law distributions, argues in favor of the absence of statistical aging. Experiments probing the emission intensity as a function of excitation power suggest that saturation is not achieved. Both absorption and emission of silicon nanocrystals contained in a one-dimensional silicon dioxide matrix are polarized to a high degree. Many of the results obtained in this work seem to strengthen the arguments that oxide-capped silicon quantum dots have universal properties, independently of the fabrication method, and that the greatest differences between individual nanocrystals are indeed caused by individual factors like local environment, shape and size (among others). / <p>QC 20120920</p>

Electronic power devices made of silicon carbide promisesuperior performance over today's silicon devices due toinherent material properties. As a result of the material'swide band gap of 3.2eV, high thermal conductivity, itsmechanical and chemical stability and a high critical electricfield, 4H-silicon carbide devices have the potential to be usedat elevated temperatures and in harsh environments. Shortercarrier lifetimes and a reduction in the necessary width of thelow-doped drift zone in silicon carbide devices compared totheir silicon counterparts result in faster switching speedsand lower switching losses and thus in much more efficientpower devices. High-voltage 4H-silicon carbide diodes have been fabricatedin a newly developed processing sequence, using standardsilicon process equipment. Epitaxial layers grown by chemicalvapor deposition (CVD) on commercial 4H-silicon carbidesubstrates were used as starting material for both mesa-etchedepitaxial and implanted p+n-n+ planar diodes, Schottky diodesand merged pn-Schottky (MPS) diodes, together with additionaltest structures. The device metallization was optimized to givea low contact resistivity on implanted and epitaxial layers anda sufficiently high Schottky barrier with a singlemetallization scheme. Different high-field termination designshave been tested and breakdown voltages of up to 4 kV onimplanted, field-ring terminated diodes were achieved,corresponding to 80% of the critical electric field. A 5kVepitaxial diode design with a forward voltage drop of 3.5V at acurrent density of 100Acm-2 equipped with an implanted junctiontermination extension (JTE) was also fabricated. A new measurement setup was designed and built with thecapability of measuring current-voltage and capacitance-voltagecharacteristics of semiconductor devices at reverse biases upto 10kV. Together with these electrical measurements, theresults of other characterization techniques were used toidentify performance limiting defects in the fabricated siliconcarbide diodes. Increased forward voltage drop of bipolardevices during on-state operation was studied and it was shownthat the stacking faults causing forward degradation arevisible in scanning electron microscopy. With the help ofsynchrotron white-beam X-ray diffraction topographs (SWBXT),electron beam induced current (EBIC) and electroluminescencemeasurements of silicon carbide diodes, the role of screwdislocations as a dominant source of device failure in the formof localized microplasma breakdown was identified. Screwdislocations with and without open core have been found tocause a 20-80% reduction in the critical electric field of4H-silicon carbide diodes, both for low-voltage (150V) andhigh-voltage (~5kV) designs. While micropipes have almost beeneliminated from commercial silicon carbide material,closed-core screw dislocations are still abundant withdensities in the order of 10000cm-2 in state-of-the-art siliconcarbide epitaxial layers.

When the size of display panel increased, the RC delay of TFTs became serious.In order to solve this problem, it is necessary to incorporate a high dielectric (high-k) material used as the gate oxide can increase the gate oxide capacitance Co, which can induce a higher drain current and higher aperture ratio. In this study, titanium silicon oxide films were grown on amorphous silicon and poly-crystal silicon by liquid phase deposition, the addition of NH4OH in the growth solution can control the PH value and prevent the amorphous and poly-crystalline silicon over etching by HF. The physical and chemical properties of titanium silicon oxide film by means of several measuring instruments, including Fourier transform infrared spectrometer (FTIR), and X-Ray diffractometer (XRD). An Al/titanium silicon oxide/a-Si or poly-Si/Si metal-oxide-semiconductor (MOS) capacitor structure was used for the electrical measurements. After oxygen and nitrogen annealing, the leakage current is improved due to the reduction of the oxygen vacancy of titanium silicon oxide film. However, the electrical characteristics can be further improved by the postmetallization annealing treatment especially under the negative electric field. Post-metallization annealing (PMA) is to use the reaction between the aluminum contact and hydroxyl groups existed on oxide surface to form active hydrogen and diffuse through the oxide to passivate the oxide traps. Therefore, titanium silicon oxide film which treated by PMA with higher dielectric constant and lower leakage current can be obtained.

In recent years, in order to promote the MOSFET¡¦s frequency and performance, the dimension keeping scale down, we can get more transistors in the same area. But nowadays the development of the lithography technology has come to the bottleneck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed. In order to get strain from the channel, by process, deposit Si3N4 at NMOS and adopt the silicon-germanium epitaxy on source/drain by PMOS, can effective improve NMOS and PMOS electronic characteristic. Besides, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress by NMOS and strain due to uniaxial compressive stress by PMOS. By these ways, we successfully improve drain current and mobility of NMOS and PMOS. Furthermore, this study is also probing into strain silicon at low temperature, the impacts on electronic characteristic by different scattering mechanism.