Long-haul optical fiber communication system is an important infrastructure to support the latest broadband communication in the world. It is important to study a technology to improve the performance of such system, and the Return-to-Zero Differential Phase Shift Keying (RZ-DPSK) modulation attracts much attention because of its improved long distance transmission performance. One important technology of the current long-haul optical fiber communication system is the dispersion map, and it is widely deployed for already installed undersea optical fiber communication system in the world. Recently, a new dispersion map that was totally different from the map used for already deployed system was proposed, and it demonstrated advantageous performance of the long-haul RZ-DPSK transmission. Even though, the reason of the performance improvement is not investigated, and it is important to clarify the physical mechanism of the performance improvement, because it will contribute to improve the system design of the long-haul optical fiber communication systems in near future. In this master thesis, the performance of the RZ-DPSK format in the long-haul transmission system is studied. Both computer simulations and experiments are conducted to confirm the effects of various factors in the long-haul RZ-DPSK transmission system. From the theoretical study, it is pointed out that the Self-Phase Modulation (SPM) played a significant role to degrade the transmission performance of the conventional map, while it does not cause so significant degradation in the new map. The effects of the SPM and the Cross-Phase Modulation (XPM) with the conventional map are investigated through the experimental study.

The incorporation of rare earth-V (RE-V) semimetallic nanoparticles embedded in III-V compound semiconductors is of great interest for applications in solid-state devices including multijunction tandem solar cells, thermoelectric devices, and fast photoconductors for terahertz radiation sources and receivers. With regard to those nanoparticle roles in device applications and material itself, electrical and thermal properties of embedded RE-V nanoparticles, including nanoscale morphology, electronic structure, and electrical and thermal conductivity of such nanoparticles are essential to be understood to engineer their properties to optimize their influence on device performance. To understand embedded RE-V semimetallic nanostructures in III-V compound semiconductors, nanoscale characterization tools are essential for analysis their properties incorporated in compound semiconductors. In this dissertation, we used atomic force microscopy (AFM) with other secondary detection tools to investigate nanoscale material properties of semimetallic RE-V and GaAs heterostructures, grown by molecular beam epitaxy. We used scanning capacitance microscopy and conductive AFM techniques to understand electronic and electrical properties of ErAs/GaAs heterostructures. For the electrical properties, this thesis investigates details of statistical analysis of scanning capacitance and local conductivity images contrast to provide insights into (i) nanoparticle structure at length scales smaller than the nominal spatial resolution of the scanned probe measurement, and (ii) both lateral and vertical nanoparticle morphology at nanometer to atomic length scales, and their influence on electrical conductivity. To understand thermal properties of ErAs nanoparticles, in-plane and cross-sectional plane of ErAs/GaAs superlattice structure were investigated with a scanning probe microscopy technique implemented with 3[omega] method for thermal measurement. By performing detailed numerical modeling of thermal transport between thermal probe tip and employed samples, and estimation of additional phonon scattering induced by ErAs nanoparticles, we could understand influences of ErAs nanoparticles on the host GaAs thermal conductivity. Investigation of ErAs semimetallic nanostructure embedded in GaAs matrix with scanned probe microscopy provided detailed understanding of their electronic, electrical and thermal properties. In addition, this dissertation also demonstrates that an atomic force microscope with secondary detection techniques is promising apparatus to understand and investigate intrinsic properties of nanostructure materials, nanoscale charge transports, when the system is combined with detailed modeling and simulations. / text

abstract: Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the number of cores increases. While making caches scalable is still an important research problem, some researchers are exploring the possibility of a more power-efficient SRAM called scratchpad memories or SPMs. SPMs consume significantly less area, and are more energy-efficient per access than caches, and therefore make the design of on-chip memories much simpler. Unlike caches, which fetch data from memories automatically, an SPM requires explicit instructions for data transfers. SPM-only architectures are thus named as software managed manycore (SMM), since the data movements of such architectures rely on software. SMM processors have been widely used in different areas, such as embedded computing, network processing, or even high performance computing. While SMM processors provide a low-power platform, the hardware alone does not guarantee power efficiency, if applications on such processors deliver low performance. Efficient software techniques are therefore required. A big body of management techniques for SMM architectures are compiler-directed, as inserting data movement operations by hand forces programmers to trace flow of data, which can be error-prone and sometimes difficult if not impossible. This thesis develops compiler-directed techniques to manage data transfers for embedded applications on SMMs efficiently. The techniques analyze and find out the proper program points and insert data movement instructions accordingly. The techniques manage code, stack and heap data of applications, and reduce execution time by 14%, 52% and 80% respectively compared to their predecessors on typical embedded applications. On top of managing local data, a technique is also developed for shared data in SMM architectures. Experimental results show it achieves more than 2X speedup than the previous technique on average. / Dissertation/Thesis / Doctoral Dissertation Computer Science 2017

This thesis deals with the development of scanning probe microscopes. Mechanical requirements for microscopes using measuring methods of scanning tunneling microscopy (STM) and atomic force microscopy (AFM) under enviroments of an ultrahigh vacuum (UHV) and variable temperatures are specified. Mechanical designs of two microscopes are discussed and their control electronics described. A special chapter is devoted to description of linear piezo manipulators and mechanical design of these prototypes.

In this thesis, the growth of 2D materials, in particular graphene and FeO2 on crystalline supports, is studied by a multitude of surface-sensitive techniques. The mechanisms of graphene growth in ultra-high vacuum and high Ar pressure are explored, and a simple device for the manufacturing of high-quality, monocrystalline graphene on SiC is described. The electronic and chemical properties of B and N dopants on graphene are characterized by means of STM/AFM with CO-functionalized tips and supported by DFT calculations. The chemical interaction of a probe molecule (FePc) with doped graphene is also investigated. The long-standing controversy of the so-called "biphase" reconstruction of α - Fe2O3(0001) is resolved by the discovery of a complete FeO2 overlayer in this phase. The structure of this overlayer is investigated by means of STM, LEEM and DFT calculations. A thorough description of the routes to obtain single phases over the whole surface of α - Fe2O3(0001) is provided.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第13818号 / 工博第2922号 / 新制||工||1432(附属図書館) / 26034 / UT51-2008-C734 / 京都大学大学院工学研究科材料工学専攻 / (主査)教授 酒井 明, 教授 田中 功, 教授 中村 裕之 / 学位規則第4条第1項該当

Scanning probe microscopy techniques were used to investigate the desorption of hydrogen passivated silicon to form SiO2 etch masks The application of the etch masks were planned on being used to manufacture silicon nanowires. Low concentration hydrofluoric acid was used to passivate the surface. The surface was selectively depassivated by SPM techniques. Scanning tunneling microscopy (STM) and atomic force microscopy (AFM) were used to create the masks. The STM system used was found to desorb hydrogen from the surface faster than the STM could image and was considered incapable in the configuration investigated. This led to the use of atomic force microscopy (AFM). Using a conductive tip in contact mode, lithography on the passivated surface was performed. The topography of the lithography was compared to similar works and found to be similar in size. The width was found to be 80nm and the thickness 1nm. The depassivated layers were confirmed to be oxide through electronic force microscopy (EFM). Finally, voltages were swept with the tip in contact with the surface to find the bandgap of the oxide. It was found that the voltage sweeps were severely modifying the tip along with producing inconsistent desorption thicknesses ranging from 0.2 to 12nm. Despite the results from the voltage sweeps, the lithography procedure performed using the AFM was found to be successful.

The Telescopio San Pedro Martir project intends to construct a 6.5m telescope to be installed at the Observatorio Astronomico Nacional in the Sierra San Pedro Martir in northern Baja California, Mexico. The project is an association of Mexican institutions, lead by the Instituto Nacional de Astrofisica, Optica y Electronica and the Instituto de Astronomia at the Universidad Nacional Autonoma de Mexico, in partnership with the Smithsonian Astrophysical Observatory and the University of Arizona's Department of Astronomy and Steward Observatory. The project is currently in the planning and design stage. Once completed, the partners plan to operate the MMT and TSPM as a binational astrophysical observatory.

Real-time computing is not just fast computing but time-predictable computing. Many tasks in safety-critical embedded real-time systems have hard real-time characteristics. Failure to meet deadlines may result in the loss of life or in large damages. Known of Worst Case Execution Time (WCET) is important for reliability or correct functional behavior of the system. As multi-core processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multi-core chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multi-cores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimate statically. We propose an approach to analyzing Worst Case Execution Time (WCET) for multi-core processors with shared L2 instruction caches by using a model checking based method. Our experiments indicate that compared to the static analysis technique based on extended ILP (Integer Linear Programming), our approach improves the tightness of WCET estimation more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multi-core timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors. At the same time, improving the average-case performance and energy efficiency has also been important for real-time systems. Recently, Hybrid SPM-Cache (HSC) architectures by combining caches and Scratch-Pad Memories (SPMs) have been increasingly used in commercial processors and research prototypes. Our research explores HSC architectures for real-time systems to reconcile time predictability, performance, and energy consumption. We study the energy dissipation of a number of hybrid on-chip memory architectures by combining both caches and Scratch-Pad Memories (SPM) without increasing the total on-chip memory size. Our experimental results indicate that with the equivalent total on-chip memory size, several hybrid SPM-Cache architectures are more energy-efficient than either pure software controlled SPMs or pure hardware-controlled caches. In particular, using the hybrid SPM-cache to store both instructions and data can achieve the best energy efficiency. However, the SPM allocation for the HSC architecture must be aware of the cache to harness the full potential of the HSC architecture. First, we propose and evaluate four SPM allocation strategies to reduce WCET for hybrid SPM-Caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache aware and WCET-oriented SPM allocation can maximally reduce the WCET with minimum or even positive impact on the average-case execution time (ACET). Moreover, we explore four SPM allocation algorithms to maximize performance on the HSC architecture, including three heuristic-based algorithms, and an optimal algorithm based on model checking. Our experiments indicate that the Greedy Stack Distance based Allocation (GSDA) can run efficiently while achieving performance either the same as or close to the optimal results got by the Optimal Stack Distance based Allocation (OSDA). Last but not the least, we extend the two stack distance based allocation algorithms to GSDA-E and OSDA-E to minimize the energy consumption of the HSC architecture. Our experimental results show that the GSDA-E can also reduce the energy either the same as or close to the optimal results attained by the OSDA-E, while achieving performance close to the OSDA and GSDA.

Real-time systems often use SPM instead of cache, because SPM allows a program¡¦s run time to be more predictable. Real-time system need predictable runtimes, because they must schedule programs to finish within specific deadlines. A deadline should be larger than its program¡¦s worst-case execution time (WCET). Our laboratory is conducting ongoing research into scratchpad memory allocation (SPM) for reducing the WCET of a program. Compared to our previous work, this current thesis improves our memory model, our allocation algorithms, our real-time support, and our measurement benchmarks and platform. Our key accomplishments in this paper are to: 1) add, for the first time in the literature, true WCETmeas analysis to an SPM allocator, 2) to modestly improve the performance of our previous allocator, and 3) to greatly increase the applicability over that allocator, by extending the method to support recursive programs.