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151	High-Speed Programmable FPGA Configuration Memory Access Using JTAG Gruwell, Ammon Bradley 01 April 2017 (has links) Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications. FPGA JTAG scrubbing fault injection radiation testing laser testing C++ Python BYU configuration readback reliability SEU Xilinx bitstream upset mitigation hardware software high speed configuration memory CRAM SRAM Joint Test Action Group ionizing radiation space aerospace interface serial ARM processor architecture programmable logic MicroZed Zynq Linux Electrical and Computer Engineering
152	Advancing cyber security with a semantic path merger packet classification algorithm Thames, John Lane 30 October 2012 (has links) This dissertation investigates and introduces novel algorithms, theories, and supporting frameworks to significantly improve the growing problem of Internet security. A distributed firewall and active response architecture is introduced that enables any device within a cyber environment to participate in the active discovery and response of cyber attacks. A theory of semantic association systems is developed for the general problem of knowledge discovery in data. The theory of semantic association systems forms the basis of a novel semantic path merger packet classification algorithm. The theoretical aspects of the semantic path merger packet classification algorithm are investigated, and the algorithm's hardware-based implementation is evaluated along with comparative analysis versus content addressable memory. Experimental results show that the hardware implementation of the semantic path merger algorithm significantly outperforms content addressable memory in terms of energy consumption and operational timing. Computational semantics Graph theory Hardware algorithms Attack detection Distributed internet security Packet classification Intrusion detection Semantic association Semantic networks Content addressable memory SRAM-based trie pipelines Hardware-based trie pipelines Computational intelligence Neural networks Parametric optimization Genetic algorithms Self-organizing maps Ensemble intelligence Firewalls Routing Packet filters Cyber intelligence (Computer security) Algorithms Cyberterrorism Denial of service attacks Anomaly detection (Computer security)

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High-Speed Programmable FPGA Configuration Memory Access Using JTAG

Advancing cyber security with a semantic path merger packet classification algorithm