Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Confiabilidade é um parâmetro de projeto importante para aplicações criticas tanto na Terra como também no espaço. Os FPGAs baseados em memoria SRAM são atrativos para implementar aplicações criticas devido a seu alto desempenho e flexibilidade. No entanto, estes FPGAs são susceptíveis aos efeitos da radiação tais como os erros transientes na memoria de configuração. Além disso, outros efeitos como o envelhecimento (aging) ou escalonamento da tensão de alimentação (voltage scaling) incrementam a sensibilidade à radiação dos FPGAs. Nossos resultados experimentais mostram que o envelhecimento e o escalonamento da tensão de alimentação podem aumentar ao menos duas vezes a susceptibilidade de FPGAs baseados em SRAM a erros transientes. Estes resultados são inovadores porque estes combinam três efeitos reais que acontecem em FPGAs baseados em SRAM. Os resultados podem guiar aos projetistas a prever os efeitos dos erros transientes durante o tempo de operação do dispositivo em diferentes níveis de tensão. A correção da memoria usando a técnica de scrubbing é um método efetivo para corrigir erros transientes em memorias SRAM, mas este método impõe custos adicionais em termos de área e consumo de energia. Neste trabalho, nos propomos uma nova técnica de scrubbing usando a redundância interna a nível de quadros chamada FLR- scrubbing. Esta técnica possui mínimo consumo de energia sem comprometer a capacidade de correção. Como estudo de caso, a técnica foi implementada em um FPGA de tamanho médio Xilinx Virtex-5, ocupando 8% dos recursos disponíveis e consumindo seis vezes menos energia que um circuito corretor tradicional chamado blind scrubber. Além, a técnica proposta reduz o tempo de reparação porque evita o uso de uma memoria externa como referencia. E como outra contribuição deste trabalho, nos apresentamos os detalhes de uma plataforma de injeção de falhas múltiplas que permite emular os erros transientes na memoria de configuração do FPGA usando reconfiguração parcial dinâmica. Resultados de campanhas de injeção são apresentados e comparados com experimentos de radiação acelerada. Finalmente, usando a plataforma de injeção de falhas proposta, nos conseguimos analisar a efetividade da técnica FLR-scrubbing. Nos também confirmamos estes resultados com experimentos de radiação acelerada. / Reliability is an important design constraint for critical applications at ground-level and aerospace. SRAM-based FPGAs are attractive for critical applications due to their high performance and flexibility. However, they are susceptible to radiation effects such as soft errors in the configuration memory. Furthermore, the effects of aging and voltage scaling increment the sensitivity of SRAM-based FPGAs to soft errors. Experimental results show that aging and voltage scaling can increase at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These findings are innovative because they combine three real effects that occur in SRAM-based FPGAs. Results can guide designers to predict soft error effects during the lifetime of devices operating at different power supply voltages. Memory scrubbing is an effective method to correct soft errors in SRAM memories, but it imposes an overhead in terms of silicon area and energy consumption. In this work, it is proposed a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLRscrubbing) with minimum energy consumption overhead without compromising the correction capabilities. As a case study, the FLR-scrubbing controller was implemented on a mid-size Xilinx Virtex-5 FPGA device, occupying 8% of available slices and consumes six times less energy per scrubbed frame than a classic blind scrubber. Also, the technique reduces the repair time by avoiding the use of an external golden memory for reference. As another contribution, this work presents the details of a Multiple Fault Injection Platform that emulates the configuration memory upsets of an FPGA using dynamic partial reconfiguration. Results of fault injection campaigns are presented and compared with accelerated ground-level radiation experiments. Finally, using our proposed fault injection platform it was possible to analyze the effectiveness of the FLR-scrubbing technique. Accelerated radiation tests confirmed these results.

User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Methods for testing commercial off-the-shelf (COTS) digital devices at varying levels of complexity is presented and discussed as well as the results for testing a COTS SRAM, FRAM, and SoC using these methodologies in a pulsed dose rate environment at Little Mountain Test Facility (LMTF) and neutron testing at Los Alamos Neutron Science Center (LANSCE). Investigations at LMTF revealed a dependence in all three devices on the integrated dose of a single pulse of radiation, implying that the duration of radiation plays a significant role in the response. The test infrastructure necessary to dynamically access an FRAM at LMTF and time the access with the pulse of radiation allowed for the discovery of a new FRAM failure mode where an entire word of the FRAM becomes corrupted as well as selecting between two different failure modes based on the timing of the pulse. A novel component-based testing methodology for testing complicated SoCs is presented and used to report on the cross-sections of several components on the Xilinx MPSoC, including its DMA which has not previously been reported.

No description available.

The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This form of computing consists of a Look-Up Table (LUT) which is basically memory array mapped with a function; the computations thereafter consist of essentially read operations. An MBC framework requires very fast and low power read operations. Moreover, the cells need to be read stable as major part of the computation is done by reading the LUTs mapped in the SRAM array. Design and measurement of a prototype MBC test-chip with SRAM system optimized for read-heavy applications is presented in this thesis. For this purpose, a prototype MBC system was designed and taped out. Essential study of the write-ability of the core LUT is also presented. The core memory array for function table mapping was characterized for leakage, write-ability and power saving associated with pulsed read mode.

Process variability is the pivotal factor impacting the design of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electrical and physical properties of transistors and interconnects, the building blocks of integrated circuits, are prone to significant variations that directly impact the performance and power consumption of the fabricated devices, severely impacting the manufacturing yield. However, the large number of the transistors on a single chip adds even more challenges for the analysis of the variation effects, a critical task in diagnosing the cause of failure and designing for yield. Reliable and efficient statistical analysis methodologies in various design phases are key to predict the yield before entering such an expensive fabrication process. In this thesis, the impacts of process variations are examined at three different levels: device, circuit, and micro-architecture. The variation models are provided for each level of abstraction, and new methodologies are proposed for efficient statistical analysis and design under variation. At the circuit level, the variability analysis of three crucial sub-blocks of today's system-on-chips, namely, digital circuits, memory cells, and analog blocks, are targeted. The accurate and efficient yield analysis of circuits is recognized as an extremely challenging task within the electronic design automation community. The large scale of the digital circuits, the extremely high yield requirement for memory cells, and the time-consuming analog circuit simulation are major concerns in the development of any statistical analysis technique. In this thesis, several sampling-based methods have been proposed for these three types of circuits to significantly improve the run-time of the traditional Monte Carlo method, without compromising accuracy. The proposed sampling-based yield analysis methods benefit from the very appealing feature of the MC method, that is, the capability to consider any complex circuit model. However, through the use and engineering of advanced variance reduction and sampling methods, ultra-fast yield estimation solutions are provided for different types of VLSI circuits. Such methods include control variate, importance sampling, correlation-controlled Latin Hypercube Sampling, and Quasi Monte Carlo. At the device level, a methodology is proposed which introduces a variation-aware design perspective for designing MOS devices in aggressively scaled geometries. The method introduces a yield measure at the device level which targets the saturation and leakage currents of an MOS transistor. A statistical method is developed to optimize the advanced doping profiles and geometry features of a device for achieving a maximum device-level yield. Finally, a statistical thermal analysis framework is proposed. It accounts for the process and thermal variations simultaneously, at the micro-architectural level. The analyzer is developed, based on the fact that the process variations lead to uncertain leakage power sources, so that the thermal profile, itself, would have a probabilistic nature. Therefore, by a co-process-thermal-leakage analysis, a more reliable full-chip statistical leakage power yield is calculated.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.