<p>This  report  is  a  part  of  a  master  thesis  project  done  at  Ericsson  Linköping  incooperation with Linköpings Tekniska Högskola (LiTH). This project is divided intwo different parts.  The first part is to create a measurement node that collectsand processes data from network time protocol servers.   It is used to determinethe  quality  of  the  IP  network  at  the  node  and  detect  potential  defects  on  usedtimeservers or nodes on the networks.The second assignment is to analyze the collected data and further improve theexisting synchronization algorithm.  Ip communication is not designed to be timecritical and therefore the NTP protocol needs to be complemented with additionalsignal processing to achieve required accuracy.  Real time requirements limit thecomputational complexity of the signal processing algorithm.</p>

<p>Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.</p><p>This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-<em>μ</em>m CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.</p> / Report code: LiU-TEK-LIC-2006:22

A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the metastability state problem. Some analog and digital circuits are incorporated with a true double-edge triggered Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the flip flop will not be received by the next stage if Q is in a metastable state. The number of transistors used in this implementation of True-Q flip flop is 90. Due to the overhead of circuit complexity, the time delay from Request to Acknowledge signal is 6.5ns. / Graduation date: 1995

The ability to distribute signals everywhere in a circuit with controlled and known delays is essential in large, high-speed digital systems. We present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. We show an implemention of this idea requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run. We demonstrate how this scheme fits into the boundary scan logic of a VLSI chip.

Parallel shared-memory machines with hundreds or thousands of processor-memory nodes have been built; in the future we will see machines with millions or even billions of nodes. Associated with such large systems is a new set of design challenges. Many problems must be addressed by an architecture in order for it to be successful; of these, we focus on three in particular. First, a scalable memory system is required. Second, the network messaging protocol must be fault-tolerant. Third, the overheads of thread creation, thread management and synchronization must be extremely low. This thesis presents the complete system design for Hamal, a shared-memory architecture which addresses these concerns and is directly scalable to one million nodes. Virtual memory and distributed objects are implemented in a manner that requires neither inter-node synchronization nor the storage of globally coherent translations at each node. We develop a lightweight fault-tolerant messaging protocol that guarantees message delivery and idempotence across a discarding network. A number of hardware mechanisms provide efficient support for massive multithreading and fine-grained synchronization. Experiments are conducted in simulation, using a trace-driven network simulator to investigate the messaging protocol and a cycle-accurate simulator to evaluate the Hamal architecture. We determine implementation parameters for the messaging protocol which optimize performance. A discarding network is easier to design and can be clocked at a higher rate, and we find that with this protocol its performance can approach that of a non-discarding network. Our simulations of Hamal demonstrate the effectiveness of its thread management and synchronization primitives. In particular, we find register-based synchronization to be an extremely efficient mechanism which can be used to implement a software barrier with a latency of only 523 cycles on a 512 node machine.

Thesis (Ph.D.)--McMaster University, 2004. / Supervisor: Dr. H.K. Haugen and Dr. P. Mascher. Includes bibliographical references (p. 135-143). Also available via World Wide Web.

A series of studies were guided by the principal hypothesis that it was necessary to characterize ovarian function during the seasons of the annual reproductive cycle in wapiti and that from this knowledge novel methods of exogenous control of ovarian function would be possible. To augment existing knowledge about endogenous control of ovarian function in wapiti studies were conducted to characterize ovarian follicle dynamics during the estrous season and to characterize ovarian follicular dynamics during the periods of transition into and out of the breeding season. The third study was designed to characterize ovarian follicle development and ovulation synchrony subsequent to an estrous synchronization protocol used commercially. To evaluate novel methods of exogenous control of ovarian function studies were conducted to determine if follicular wave emergence could be electively induced using hormonal or surgical treatments to evaluate novel ovarian superstimulatory treatment protocols. <p>It was concluded from the studies of ovarian function that follicle development during the breeding season was characterized by the regular and synchronous development of follicular waves and that 2, 3, or 4 waves occurred during each interovulatory interval. Transition into the breeding season was preceded by one short interovulatory interval (9 days) characterized by one wave of follicle development and a small, short-lived and hypo-functional corpus luteum. The last estrous cycle of the breeding season was similar to estrous cycles during the rut (21 days), but and transition to anestrus was marked by a failure of the dominant follicle to ovulate after luteal regression. The treatment protocol used commercially for estrous synchronization was effective, but unnecessarily long. It was concluded from the studies on exogenous control of ovarian function that follicular wave emergence could be electively induced using steroid hormones or follicle ablation and may be useful for estrus synchronization and superstimulatory protocols. The tested superstimulatory treatments were effective and had the advantage of reducing the treatment period by 6 days and the number of times the animals are handled by one third over a more conventional method. However, oocyte and embryo quality were not evaluated. <p>As a result of the studies conducted and one previous study during the anouvlatory season follicle and luteal dynamics are now known in wapiti for all seasons of the year and this knowledge will provide a template upon which other species of deer can be compared. The final two studies support the principal hypothesis. The novel methods of exogenous ovarian control tested increase the potential for success when applying reproductive technologies and the successful application of these methods in wapiti should lead to their successful use in other species of deer.

A virtual holonomic constraint (VHC) for an Euler-Lagrange Control System is a smooth relation between the configuration variables that can be made invariant through application of suitable feedback. In this thesis we investigate the role played by VHCs in the synchronization of Euler-Lagrange systems. We focus on two problems. For $N$ underactuated cart-pendulums, we design a smooth feedback that fully synchronizes the cart-pendulums while simultaneously stabilizing a periodic orbit corresponding to a desired oscillation for the pendulums. A by-product of our results is the ability to simultaneously synchronize the pendulums and stabilize the unstable upright equilibrium. The second synchronization problem investigated in this thesis is bilateral teleoperation, whereby a master robot is operated by a human while a slave robot synchronizes to the master. For two identical planar manipulators, we develop a methodology to achieve teleoperation in the presence of a hard surface, with simultaneous force control.

A virtual holonomic constraint (VHC) for an Euler-Lagrange Control System is a smooth relation between the configuration variables that can be made invariant through application of suitable feedback. In this thesis we investigate the role played by VHCs in the synchronization of Euler-Lagrange systems. We focus on two problems. For $N$ underactuated cart-pendulums, we design a smooth feedback that fully synchronizes the cart-pendulums while simultaneously stabilizing a periodic orbit corresponding to a desired oscillation for the pendulums. A by-product of our results is the ability to simultaneously synchronize the pendulums and stabilize the unstable upright equilibrium. The second synchronization problem investigated in this thesis is bilateral teleoperation, whereby a master robot is operated by a human while a slave robot synchronizes to the master. For two identical planar manipulators, we develop a methodology to achieve teleoperation in the presence of a hard surface, with simultaneous force control.

This  report  is  a  part  of  a  master  thesis  project  done  at  Ericsson  Linköping  incooperation with Linköpings Tekniska Högskola (LiTH). This project is divided intwo different parts.  The first part is to create a measurement node that collectsand processes data from network time protocol servers.   It is used to determinethe  quality  of  the  IP  network  at  the  node  and  detect  potential  defects  on  usedtimeservers or nodes on the networks.The second assignment is to analyze the collected data and further improve theexisting synchronization algorithm.  Ip communication is not designed to be timecritical and therefore the NTP protocol needs to be complemented with additionalsignal processing to achieve required accuracy.  Real time requirements limit thecomputational complexity of the signal processing algorithm.