Este trabalho apresenta e implementa um algoritmo de escalonamento para a tecnologia Foundation Fieldbus. O algoritmo denominado FFSMART escalona as mensagens de comunicação cíclica ou periódica entre os dispositivos de campo que estão no barramento fieldbus. Trata-se de um algoritmo de escalonamento pré-run-time, que permite atender às restrições de precedência dos blocos funcionais, personalizando e otimizando o uso dos recursos do sistema. O algoritmo foi implementado na linguagem de programação Visual Basic e sua validação ocorreu em um ambiente real de aplicação através de estratégias de configuração, cujos resultados foram satisfatórios. / This dissertation presents and implements a scheduling algorithm for the Foundation Fieldbus technology. The algorithm named FFSMART schedules cyclic or periodic communication messages among field devices connected to a fieldbus. The FFSMART is a pre-runtime scheduling algorithm, which allows meeting the restrictions of precedence from function blocks, customizing and optimizing the use of the system resources. The algorithm was implemented using the Visual Basic programming language and validated in a real application environment using configuration strategies, and the results were satisfactory.

Este trabalho apresenta e implementa um algoritmo de escalonamento para a tecnologia Foundation Fieldbus. O algoritmo denominado FFSMART escalona as mensagens de comunicação cíclica ou periódica entre os dispositivos de campo que estão no barramento fieldbus. Trata-se de um algoritmo de escalonamento pré-run-time, que permite atender às restrições de precedência dos blocos funcionais, personalizando e otimizando o uso dos recursos do sistema. O algoritmo foi implementado na linguagem de programação Visual Basic e sua validação ocorreu em um ambiente real de aplicação através de estratégias de configuração, cujos resultados foram satisfatórios. / This dissertation presents and implements a scheduling algorithm for the Foundation Fieldbus technology. The algorithm named FFSMART schedules cyclic or periodic communication messages among field devices connected to a fieldbus. The FFSMART is a pre-runtime scheduling algorithm, which allows meeting the restrictions of precedence from function blocks, customizing and optimizing the use of the system resources. The algorithm was implemented using the Visual Basic programming language and validated in a real application environment using configuration strategies, and the results were satisfactory.

Tourism is an important factor for economic growth. Unfortunately, the on going COVID-19 pandemic has struck hard on the tourism sector due to the lockdowns and travel restrictions. The lockdowns have also led to an increasing isolation among people which in the long term can lead to a decline in people’s psychological wellbeing.Together with Cybercom Group AB, an idea to solve this problem was to developan application with the intention to nurture the tourism sector and get people out of their homes while keeping the human interactions at a satisfactory level. The main feature of the application developed was a scheduler that carefully planned out people’s daily activities depending how crowded a specific location was. An application such as the one developed could lead to an increase in foot traffic while simultaneously decreasing the amount of physical contact between people. The result of this thesis mainly focuses on the developed application but more specifically the developed algorithms to schedule your day using crowd data. The algorithmdeveloped, the Optimal Time Slot Algorithm, averaged a crowding value of18,8% while the average of the best possible crowding value was 17,8%. / Turism är en viktig faktor för ekonomisk tillväxt. Tyvärr så har den pågående COVID-19 pandemin slagit hårt mot turismsektorn till följd av nedstängningar och restriktionerpå resande. Nedstängningarna har även lett till en ökad isolering hos personersom långsiktigt kan leda till en försämring av människors psykologiska välmående.Tillsammans med Cybercom Group AB växte en idé fram om att utveckla enapplikation som har till uppgift att främja turismsektorn och hjälpa folk att ta sig utur sina hem samtidigt som de undviker trängsel. Huvudfunktionen hos den utvecklade applikationen var en planerare som noggrantplanerar en persons dagliga aktiviteter beroende på hur mycket folk det var på denspecifika platsen vid ett visst tillfälle. En applikation likt den som utvecklats kan ledatill en ökad mängd personer i rörelse i kombination med att minska mängden fysiskkontakt mellan människor. Resultatet av detta examensarbete fokuserar huvudsakligen på den utvecklade applikationenoch specifikt de algoritmer som utvecklats för att planera din dag genomträngseldata. Den framtagna algoritmen, Optimal Time Slot Algorithm, resulteradei ett trängselsnitt på 17,8% där 18,8% var snittet av det bästa möjliga resultatet.

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This thesis presents a new unified algorithm for cluster assignment and acyclic region scheduling in a partitioned architecture, and preliminary results on its integration into an experimental retargetable code generation framework. The object of this work is twofold. Firstly, to validate for the first time, and evaluate the framework which is almost automatic, so as to gain insights into possibilities for improvement. This was done by using as a baseline for comparison, highly optimized code generated by the handcrafted compiler of Texas Instruments, the TI Code Composer Studio V2. The second objective is to compare the integrated scheduling algorithm with another well known algorithm which performs scheduling and cluster allocation in the same phase, the Unified Assign and Schedule (UAS) algorithm. The computational complexity of the two algorithms is comparable. The components of the framework experimented with here are (a) a tree transformer generator, which takes as input, a description of the instruction set of the target architecture in the form of a regular tree grammar augmented with actions and attributes, and outputs a data dependency directed acyclic graph, (b) the well known public domain IMPACT front end for C, (c)a microarchitecture description module which uses a modification of the HMDES architecture description language of the TRIMARAN project, to include cluster information, and (d) a combined cluster allocator and acyclic region scheduler and a register allocator designed and implemented by us. Experiments have been carried out on creating the proper interfaces for all the modules to work together, and the targeting of the tool to the Texas Instruments TMS320c62x architecture to establish the feasibility of this approach. We present the results of our implementation on a set of benchmarks and some sorting programs and compare them with those obtained from the state-of-the-art TI compiler. The performance without software pipelining shows that our executables take on the average 1.4 times the execution time as that of those generated by the TI compiler. The integrated scheduling algorithm proposed in this thesis performs at least as well as the UAS algorithm and sometimes better by as much as 9 % in terms of the parallelism obtained.

Cette thèse explore les problèmes liés à l'ordonnancement concurrent dans le contexte des applications massivement parallèle, de deux points de vue: le coté mémoire (en particulier la mémoire cache) et le coté tolérance aux fautes.Avec l'avènement récent des architectures dites many-core, tels que les récents processeurs multi-coeurs, le nombre d'unités de traitement augmente de manière importante.Dans ce contexte, les avantages fournis par les techniques d'ordonnancements concurrents ont été démontrés à travers de nombreuses études.L'ordonnancement concurrent, aussi appelé co-ordonnancement, consiste à exécuter les applications de manière concurrente plutôt que les unes après les autres, dans le but d'améliorer le débit global de la plateforme.Mais le partage des ressources peut souvent générer des interférences.Une des solutions pour réduire de manière importante ces interférences est le partitionnement de cache.À travers un modèle théorique, des simulations et des expériences sur une plateforme existante, nous montrons l'utilité et l'importance du co-ordonnancement quand nos stratégies de partitionnement de cache sont utilisées.De plus, avec ce nombre croissant de processeurs, la probabilité d'une panne augmente également.L'efficacité des techniques de co-ordonnancement a été démontrée dans un contexte sans pannes, mais les plateformes massivement parallèles sont confrontées à des pannes fréquentes, et des techniques de tolérance aux fautes doivent être mise en place pour améliorer l'efficacité de ces plateformes.Nous étudions la complexité du problème avec un modèle théorique, nous concevons des heuristiques et nous effectuons un ensemble complet de simulations avec un simulateur de pannes, qui démontre l'efficacité des heuristiques proposées. / This thesis explores co-scheduling problems in the context of large-scale applications with two main focus: the memory side, in particular the cache memory and the resilience side.With the recent advent of many-core architectures such as chip multiprocessors (CMP), the number of processing units is increasing.In this context, the benefits of co-scheduling techniques have been demonstrated. Recall that, the main idea behind co-scheduling is to execute applications concurrently rather than in sequence in order to improve the global throughput of the platform.But sharing resources often generates interferences.With the arising number of processing units accessing to the same last-level cache, those interferences among co-scheduled applications becomes critical.In addition, with that increasing number of processors the probability of a failure increases too.Resiliency aspects must be taking into account, specially for co-scheduling because failure-prone resources might be shared between applications.On the memory side, we focus on the interferences in the last-level cache, one solution used to reduce these interferences is the cache partitioning.Extensive simulations demonstrate the usefulness of co-scheduling when our efficient cache partitioning strategies are deployed.We also investigate the same problem on a real cache partitioned chip multiprocessors, using the Cache Allocation Technology recently provided by Intel.In a second time, still on the memory side, we study how to model and schedule task graphs on the new many-core architectures, such as Knights Landing architecture.These architectures offer a new level in the memory hierarchy through a new on-packagehigh-bandwidth memory. Current approaches usually do not take intoaccount this new memory level, however new scheduling algorithms anddata partitioning schemes are needed to take advantage of this deepmemory hierarchy.On the resilience, we explore the impact on failures on co-scheduling performance.The co-scheduling approach has been demonstrated in a fault-free context, but large-scale computer systems are confronted by frequent failures, and resilience techniques must be employed for large applications to execute efficiently. Indeed, failures may create severe imbalance between applications, and significantly degrade performance.We aim at minimizing the expected completion time of a set of co-scheduled applications in a failure-prone context by redistributing processors.

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No description available.

Apresenta-se um framework que permite a caracterização, conformação e escalonamento de todas as categorias de serviços A TM, dentro do ambiente de usuário (CEP). Propõem-se um modelo de tráfego otimizado para este ambiente que oferece condições de garantias de QoS individuais para fluxos VBR, tempo real ou não, CBR, ABR e UBR. O modelo proposto, denominado de PCSTS (priority class services traffic shaping), inclui um módulo que permite a obtenção do descritor de tráfego de fluxos desconhecidos. Os fluxos são conformados de forma individual, e em tempo real, segundo um conformador baseado num algoritmo de escalonamento virtual duplo baseado no GCRA do ITU/ ATM Forum. Para a multiplexação dinâmica dos diferentes fluxos do ambiente de usuário, no enlace de acesso, é proposto um algoritmo de escalonamento EDD, modificado através de um sinal de realimentação entre conformador e escalonador, e desta forma tem-se condições de oferecer garantias de limite de atraso e jitter para fluxos individuais de serviços rt-VBR ou nrt-VBR. São apresentadas simulações, tanto da caracterização dos fluxos desconhecidos como da arquitetura do escalonador, que comprovam o comportamento esperado do modelo de tráfego PCSTS. / We present a framework that enhances the characterization, shaping and scheduling of ATM traffic flows for ali ATM service categories in the customer prernise equipment (CPE) environment. We propose an optirnized traffic model, capable to guarantee QoS parameters at per connection levei for VBR services, real time or not, CBR, ABR and UBR services. The model proposed, narned PCSTS (priority classes services traffic shaping), includes a module that performs the characterization of services with unknown traffic descriptor. The flows are shaped individually, in real time, through a shaper based on the double discrete time scheduling algorithm of the GCRA from ITU/ ATM Forum. For the dynarnic multiplexing of the different service flows , at the link levei, a modified EDD scheduling algorithm is proposed with a feedback signal between the scheduling and shaping modules. As a result, it is demonstrated that it is possible to grant jitter and delay bounds for the rt-VBR and nrt-VBR services. We present simulations of the traffic characterization module and of the scheduling architecture, for different services, which confirms the expected behavior of the PCSTS model.