Gold wire bonding typically uses 60 KHz ultrasonic frequency. Studies have been reported that increasing ultrasonic frequency from 60KHz to 120KHz can decrease bonding time, lower bonding temperature, and/or improve the bondability of Au metalized organic substrates. This thesis presents a systematic study of the effects of 120 KHz ultrasonic frequency on the reliability of fine pitch gold wire bonding. Two wire sizes, 25.4 and 17.8 μm in diameter (1.0 and 0.7 mil, respectively) were used. The gold wires were bonded to metalized pads over organic substrates with five different metallization. The studies were carried out using a thermosonic ball bonder that is able to easily switch from ultrasonic frequency from 60 KHz to 120 KHz by changing the ultrasonic transducer and the ultrasonic generator. Bonding parameters were optimized through design of experiment methodology for four different cases: 60 KHz with 25.4 μm wire, 60 KHz with 17.8 μm wire, 120 KHz with 25.4 μm wire, and 120 KHz with 17.8 μm wire. The integrity of wire bonds was evaluated by the wire pull and the ball bond shear tests. With the optimized bonding parameters, over 2,250 bonds were made for each frequency and wire size. The samples were then divided into three groups. The first group was subjected to temperature cycling from -55°C to +125°C with one hour per cycle for up to 1000 cycles. The second group was subject to thermal aging at 125°C for up to 1000 hours. The third group was subject to humidity at 85°C/85% relative humidity (RH) for up to 1000 hours. The bond integrity was evaluated through the wire pull and the ball shear tests immediately after bonding, and after each 150, 300, 500, and 1000 hours time interval in the reliability tests. The pull and shear data are then analyzed to compare the wire bond performance between different ultrasonic frequencies.

As the transistor count per chip in computer microprocessors surpasses one billion, the semiconductor industry has become more and more concerned with meeting processor’s power requirements. This poses a design challenge for the power supply module, especially when the processor operates at low voltage range. For example, the electrical requirement for the newest Intel microprocessors has exceeded 100A with an input voltage of approximately 1V. To overcome this problem, multiphase DC-to-DC converters encased in a voltage regulator module (VRM) have become the standard means of supplying power to computer microprocessor. This study proposes a new topology for the multiphase DC-to-DC converter for powering microprocessors. The new topology accepts 12 V input, and outputs a steady state voltage of 1 V with a maximum output current of 40 A. The proposed topology aims to improve the input and output characteristics of the basic multiphase “buck” converter, along with an improved efficiency, line regulation, and load regulation. To explore the feasibility of such a topology, open-loop computer simulation and closed-loop hardware tests were performed. On open-loop simulation, OrCad pspice was used to verify design calculations and evaluate its performance. Then the closed-loop hardware prototype was tested to compare the circuit performance with those values obtained from simulation. The result shows the proposed topology improvement of efficiency, board size, output ripple, and regulations.

In the last 15 years, an immense amount of research has gone into developing high efficiency Gallium Nitride based light emitting diodes (LED). These devices have become increasingly popular in LED displays and solid state lighting. Due to the large difference in refractive index between GaN and Air, a significant amount of light reflects at the boundary and does not escape the device. This drawback decreases external quantum efficiency (EQE) by minimizing light extraction. Scientists and engineers continue to develop creative solutions to enhance light extraction. Some solutions include surface roughening, patterned sapphire substrates, and reflective layers. This study proposes to increase external quantum efficiency and optimize light extraction efficiency of several LED structures using finite difference time domain analysis (FDTD). The structures under investigation include GaN based LEDs with nanoscale top gratings, patterned sapphire substrates in combination with SiO2 nanorod arrays, and reflective surfaces below and above the sapphire substrate. First, we optimize GaN based nanoscale top gratings and increase light extraction by 17.8%. Next, we simulate ITO based top gratings and enhance light extraction by 40%. Third, we optimize patterned sapphire substrate period and width and the vertical position of a SiO2 nanorod array. We achieve as high as 51.8% improvement in light extraction. Finally, we increase light extraction by 160% with the use of a silver reflection layer.

This paper studies the optical properties of a GaN Laser Diode (LD). Through simulation, the GaN LD is optimized for the best optical confinement factor. It is found that there are optimal thicknesses of each layer in the diode that yield the highest optical confinement factor. There is a strong relationship between the optical confinement factor and lasing threshold—a higher optical confinement factor results in a lower lasing threshold. Increasing optical confinement improves lasing efficiency. Blue LDs are important to the future of lighting sources as they represent the final color in the RGB spectrum that does not have a high efficiency solution. The modeled GaN LD emits blue light at around ~450nm. Each layer of the GaN LD is drawn in a model simulation program called LaserMOD created by RSOFT Design Group, Inc. By properly modifying the properties of each layer, an accurate model of the GaN LD is created and then simulated. This paper describes the steps taken to properly model and optimize the GaN LD in the 1D and 2D models.

No description available.

To keep downsizing transistors, new materials must be explored since traditional 3D materials begin to experience tunneling and other problematic physical phenomena at small sizes. 2D materials are appealing due to their thinness and bandgap. The relatively weak van der Waals forces between layers in 2D materials allow easy exfoliation and device fabrication but they also result in poor heat transfer to the substrate, which is the main path for heat removal. The impaired thermal coupling is exacerbated in few-layer devices where heat dissipated in the layers further from the substrate encounters additional interlayer thermal resistance before reaching the substrate, which results in self-heating and degradation of mobility. This study explores the electro-thermal properties of five materials (MoS2, MoSe2, WS2, WSe2, and 2D black phosphorous) which have been identified as possible replacements for Si in future sub-5-nm channel-length devices. We have developed a coupled electro-thermal model to calculate device mobility. The carrier wavefunctions and distribution are obtained from solving the coupled Schrodinger and Poisson equations in the cross-plane direction. The screening length is then calculated from the screening wavenumber. We calculate TBC for each layer in the stack into the substrate from a model based on first-principles phonon dispersion. We determine the local temperature in each layer from a ratio of its dissipated energy and its TBC. We simulate various devices with self-heating (Delta T does not equal 0, where Delta T is the temperature rise of the few-layer device) under several parameters and examined the effects on mobility and change in device temperature. The effects are compared to the isothermal case (Delta T = 0). We observe that self-heating has a significant effect on temperature rise, layer-wise drain current, and effective mobility. Black phosphorous performs the best electrothermally and WS2 performs the worst overall. This thesis will inform future thermally aware designs of nanoelectronic devices based on 2D materials.

Photolithography is the most complex of the operations involved in the fabrication of a wafer, and it requires the greatest precision. Photolithography is used to create multiple layers of circuit patterns on a chip. Traditionally, wafer fab operations, and in particular, those performed in the photolithography processing area, have always presented challenging scheduling and control problems. Some of the characteristics that make the photolithography processing area difficult to schedule are as follows: reentrant flow, unpredictable yield and rework time at critical operations, shared resources such as reticles, rapidly changing technologies, and lot dedication for steppers and scanners for critical layers. This processing area, where wafers are exposed using scanners or steppers, typically, comprises the bottleneck workstations. Also, the numbers of reticles available for a given layer of product type are limited. Consequently, it is important to develop appropriate schedules to ensure effective utilization of the tools involved. In this study, a manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in a photolithography area consisting of steppers and scanners (tools), with each product requiring a specific reticle type, determine the sequence in which to process the lots on the tools loaded with requisite reticles, so as to minimize the cycle time. The reticles required for processing a product are known apriori and can be transferred from one tool to another. Also, the lot dedication requirement has to be met. This requirement pertains to the fact that some of the layers of a lot should be processed on the same tool. (Scanner or Stepper). The processing of other layers may not require lot dedication. These are handled accordingly. Some lots may enter into the system with the requirement of processing them urgently. (called hot lots). These are handled in the formulation of the problem as such. Two solution methodologies are presented for the above stated problem. The first methodology uses a mathematical programming based approach. For the given routes and processing times of the product types, the entire problem is formulated as an Integer program. This integer program uses the start time of the jobs at various operations and the availability of reticles as variables, among others. The objective is to reduce the cycle time of the lots released into the system. The cycle time of a lot is defined as the time that a lot spends in the system. Results from the experimentation for integer program show that the computation time for solving small size problems is very high. A methodology is presented to solve this model efficiently. The second methodology consists of the development of a new dispatching rule for scheduling lots in the photolithography processing area. This along with the other dispatching rules discussed in the literature are implemented using the Autosched AP software to study the impact that lot dedication makes on the performance of a fab. The performance measures that are considered include throughput, cycle time, WIP and utilization of tool sets. The results are presented for 1-level, 2-level and 3-level lot dedication schemes. . It is shown that the 3- level lot dedication scheme performs the best under no preventive maintenance/breakdown case while, for the deterministic value of unscheduled breakdown times and preventive maintenance schedule used, 1-level lot dedication performed the best. Even though the 3-level lot dedication scheme is more flexible as compared to the 1–level lot dedication scheme, yet for the values of unscheduled breakdown times and preventive maintenance schedule used, the performance of the 3- level lot dedication scheme is worse than that of the 1- level lot dedication scheme. For another set of break down time values and preventive maintenance schedule, the outcome can be different. We also compare the performance of the proposed procedure with that of the dispatching rules available with the AutoSched AP software. The results indicate that the proposed procedure is consistent in generating better solutions under different operating conditions. / Master of Science

The semiconductor industry provides a host of very challenging problems in production planning and scheduling because of the unique features of the wafer fab. This research addresses the need to develop an approach, which can be used to generate optimal or near-optimal solutions to the scheduling problem of a wafer fab, by using Mathematical Programming for a general case of a wafer fab. The problem is approached in two steps. First, the number of lots of different products to be released into the system during each planning period is determined, such that the total tardiness of the product orders is minimized over the planning horizon. Second, the schedule of these lots is determined so that the cycle time of each lot released into the system is minimized. Thus, the performance measures based both on due dates and cycle time are considered. The lot release, tardiness problem is formulated as an integer linear program, and a 3-phase procedure, which utilizes a variation of the Wilkerson-Irwin algorithm, is developed. The performance of this 3-phase procedure is further improved by using insights from classical scheduling theory. The scheduling problem is formulated as a 0-1 integer linear program. An algorithm is developed for tightening the LP relaxation of this 0-1 integer linear programming model (of the scheduling problem) leading to a better performance of the branch and bound procedure used for its solution. Lagrangian relaxation is applied on a carefully chosen set of constraints in the scheduling problem, and a Lagrangian heuristic is developed for scheduling the jobs in each period of the planning horizon. Several useful insights are developed throughout to further improve the performance of the proposed algorithm. Experiments are conducted for both the tardiness and the scheduling problems. Five experiments are conducted for the tardiness problem. Each experiment has a different combination of number of products, machines, and work orders in a small sized wafer fab (2 to 6 products, 8 to 10 station families, 15 to 30 workstations, 9 to19 work orders, and 100 to 250 lots per work order). The solutions obtained by the 3-phase procedure are compared to the optimal solutions of the corresponding tardiness problems, and the tardiness per work order for the 3-phase procedure is 0% to 25% greater than the optimal solution. But the time required to obtain the optimal solution is 22 to 1074 times greater than the time required to obtain the solution through the 3-phase procedure. Thus, the 3-phase procedure can generate almost optimal solutions and requires much smaller computation time than that required by the optimal solution. Four experiments are conducted to test the performance of the scheduling problem. Each experiment has a different combination of number of products, machines, routes, bottleneck stations, processing times, and product mix entering the system each day in a small sized wafer fab (2 products, 8 station families, 18 workstations, and 8 to 10 lots released per day into the system). The solution quality of the schedule generated by the Lagrangian heuristic is compared to the solution provided by the standard dispatching rules available in practice. In each experiment, the cycle time of a product for each dispatching rule is divided by the best cycle time for that product over all the dispatching rules in that experiment. This ratio for the Lagrangian heuristic in each experiment and over all the experiments varies from 100% to 104%. For the standard dispatching rules, this ratio ranges from 100% to 120% in each experiment and also over all the experiments. The average of the ratio over all the experiments is the least for the Lagrangian heuristic. This indicates that for the experiments conducted, the Lagrangian heuristic consistently provides a solution that is, or is close to, the best solution and, hence, quite competitive when compared to the standard dispatching rules. / Master of Science

<p>III-V nanowire (NW) ensemble devices were fabricated using novel approaches to address key NW optoelectronic issues concerning electrical contacts, doping, surface effects and underlying electrostatics physics.</p> <p>NWs were first embedded in a filling medium, thus achieving low sheet resistance front contacts while preventing shunts. Various filling materials were assessed for porosity, surface roughness and thermal stability, giving Cyclotene as an ideal filing material. Sonication was also introduced as a novel method to achieve perfect planarization.</p> <p>The presence of the Cyclotene also enabled the NWs to be characterized precisely and easily by secondary ion mass spectrometry (SIMS) to give the NW dopant concentration with excellent spatial resolution. Additionally, SIMS characterization demonstrated the ability to characterize the height uniformity of individual segments in a heterostructure NW ensemble.</p> <p>The focus of the work shifted towards surface effects on NW device performance. Therefore, Poisson's equation was solved to provide a comprehensive model of NW surface depletion as a function of interface state density, NW radius and doping density. Underlying physics was examined where surface depletion was found to significantly reduce the conductivity of thin NWs, leading to carrier inversion for some.</p> <p>This model was then applied in conjunction with a transport model to fit current-voltage curves of an AlInP-passivated GaAs NW ensemble device. A 55% decrease in surface state density was achieved upon passivation, corresponding to an impressive four order of magnitude increase in the effective carrier concentration. Additionally, conventional and time-resolved photoluminescence measurements showed intensity and carrier lifetime improvement greater than 20x upon passivation.</p> <p>Finally, the model was extended to describe radial pn junction NWs with surface depletion to give radial energy band profiles for any arbitrary set of NW parameters. Specific cases were analyzed to extract pertinent underlying physics, while the built-in potential was optimized for the design for an optimal device.</p> / Doctor of Philosophy (PhD)

<p>Surface preparation and its exposure to different processing conditions is a key step in heterogeneous integration of electronics, photonics, fluidics and/or mechanical components for More-than-Moore applications. Therefore, it is critical to understand how various processing and environmental conditions affect the surface properties of bonding substrates. In this thesis, the effects of oxygen reactive-ion etching (O₂ RIE) plasma followed by storage in ambient and 98% relative humidity on some key surface properties such as roughness, water contact angle, hardness, and the elemental and compositional states of three materials – silicon (Si), silicon dioxide (SiO₂) and glass – are investigated to analyze their influence on bondability. Lower O₂ RIE plasma activation times cause low surface roughness, high surface reactivity and high hydrophilicity of Si, SiO₂ and glass. The decrease of hardness of Si and SiO₂ with increased activation time is attributed to higher surface roughness and formation of amorphous layers of Si. While contact angle and surface roughness results show correlation with bondability, the role of hardness on bondability requires further investigation. The high-resolution X-ray Photoelectron Spectroscopy (XPS) spectra of O₂ RIE treated Si, SiO₂ and glass showed the presence of Si(-O)₂ resulting in highly reactive surfaces. The high surface reactivity of Si, SiO₂ and glass obtained from oxygen plasma activation at lower activation times can result in better bondability. Also, the ambient humidity-induced Si(-OH)_x plays an important role in the hydrophilic wafer bonding of Si and SiO₂ which may require a low temperature heating.</p> / Master of Applied Science (MASc)