The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

Thesis (MScEng)--University of Stellenbosch, 2001. / ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) logic cells are discussed, and new cells developed. The expected yield of every cell is computed through a Monte Carlo analysis, and where necessary these cells are optimized for use in a complex system. A mathematical study of the Josephson junction and SQUIDs (Superconducting Quantum Interference devices) as switching elements precede a discussion on the operation of RSFQ and COSL (Complementary Output Switching Logic.) These logic families are implemented in low temperature niobium technology, and require liquid helium cooling. A 10 GHz oversampling delta modulating analogue-to-digital converter is then designed and constructed using RSFQ and COSL building blocks in a hybrid configuration. The design emphasis is on devising ways to test the operation of RSFQ with limited equipment. Yield analysis procedures on the complex system are discussed, followed by a detailed discussion on the circuit layout and layout problems. Software routines are developed to calculate the required dimensions of layout structures. / AFRIKAANSE OPSOMMING: Rapid Single Flux Quantum (RSFQ) logiese selle word bespreek, en enkele nuwe selle word ontwikkel. Die verwagte opbrengs, of kans dat 'n sel sal werk, word bereken deur 'n Monte Carlo analise. Waar nodig word selle met behulp van die analise verbeter vir gebruik in 'n komplekse stelsel. 'n Wiskundige studie van die Josephson-vlak en SQUIDs (Superconducting Quantum Interference devices) word gevolg deur 'n bespreking oor die werking van RSFQ en COSL (Complementary Output Switching Logic.) Hierdie logiese families word geïmplementeer in laetemperatuur niobiumtegnologie, en vereis vloeibare helium-verkoeling. 'n Deltamodulerende analoog-na-digitale omsetter met 'n intree-monstertempo van 10 GHz word ontwerp en vervaardig met 'n hibriede samestelling van RSFQ en COSL boublokke. Die ontwerp fokus op maniere om die werking van RSFQ teen 10 GHz te kan toets met die beperkte toerusting wat beskikbaar is. Opbrengsanalise op die komplekse stelsel word bespreek, gevolg deur 'n volledige bespreking van die stroombaanuitlegprosedure en uitlegprobleme. Roetines word in sagteware ontwikkel om die nodige dimensies van uitlegstrukture te bereken.

Thesis (MScEng)--University of Stellenbosch, 2002. / ENGLISH ABSTRACT: For space designs, just as for terrestrial applications, the appetite for more computing power is virtually insatiable. Further, like portable applications, space use implies severe power constraints. Among currently available commercial processors, the PowerPC family ranks high in Million Instructions Per Second (MIPS) per watt, but its suitability for space applications outside low-earth orbits (LEOs) may be limited by the radiation environment, particularly single ev nt effects (SEE). This thesis covers the feasibility of using the PowerPC 603e™ processor for LEO satellite applications. The PowerPC architecture is well established with an excellent roadmap, which makes for a baseline microprocessor with long-term availability and excellent software support. The evaluation board design leverages Commercial Off-The-Shelf (COTS) technologies, allowing early integration and test. It provides a clear path to upgrades and provides a high performance platform to suit multiple missions. / AFRIKAANSE OPSOMMING: Die soeke na rekenaars met hoer werkverrigting sal nooit ophou rue. Dit geld vir beide rekenaars op aarde as satelliet aanboord rekenaars. Rekenaars vir ruimte gebruik word ook streng drywingsbeperkings opgele. Die PowerPC familie vergelyk baie goed met ander verwerkers, maar hul bruikbaarheid vir ruimte toepassings kan dalk beperk word tot lae wentelbane waar die ruimte radiasie omgewing meer toeganklik is. Die skrywe behandel die bruikbaarheid van die PowerPC 603e verwerker vir lae wentelbaan satelliet gebruik. Die welgestelde argitektuur, bekombaarheid en uitstekende sagte- _ ware ondersteuning verseker 'n standvastige fondasie. Kornmersiele komponente het voorkeur geniet in die hardeware ontwerp wat spoedige ontwikkeling sowel as aanpasbaarheid verseker. Die ontwerp bied 'n hoe werkverrigting en maklik opgradeerbare oplossing vir 'n groot verskeidenheid gebruike.

Thesis (MScEng)--University of Stellenbosch, 2002. / ENGLISH ABSTRACT: After successful use of a DSP processor onboard the SUNSAT satellite, the need arose for a faster floating-point processor. A list of possible processors was generated from various selection criteria. Two suitable DSP processors were chosen, and because no radiation information was available for one of them, the decision was made to perform radiation tests on it. The procedures used to test the processor are described in detail so the same methods can be used for future radiation tests. An error detection and correction circuit was implemented to check and correct upsets in the on-chip memory of the DSP processor. This ensures that the processor code and data stays intact. / AFRIKAANSE OPSOMMING: Na suksesvolle gebruik van 'n DSP verwerker aanboord die SUNSAT satelliet het die behoefte ontstaan vir 'n vinniger wissel-punt verwerker. 'n Lys van moontlike verwerkers is opgestel met die hulp van verskeie seleksie kriteria. Twee geskikte DSP verwerkers is gekies, en omdat geen radiasie informasie vir die een beskikbaar was nie, is besluit om radiasie toetse op hom te doen. Die prosedures gebruik om die verwerker te toets word deeglik beskryf sodat dieselfde metodes in die toekom gebruik kan word. 'n Fout deteksie en korreksie baan is geimplementeer om foute in die aanboord geheue van die DSP verwerker op te spoor en te korrigeer. Dit verseker dat die verwerker se kode en data intak bly.

Thesis (MScEng) -- University of Stellenbosch, 2004. / ENGLISH ABSTRACT: In a pioneering project for the University of Stellenbosch, and indeed South Africa, an automatic music transcription system was designed to explore the underlying theory, concepts and problematies of polyphonic music transcription. Automatic music transcription involves knowledge from the fields of acoustics, music theory, digital signal processing and information theory. The key concepts from these contributing fields as they relate to transcription systems are described in overview. A transcription system is then developed which includes components for FFT-based multipitch estimation, basic post-processing, estimation of the degree of polyphony, key determination, note duration quantisation and score output. The operation of the system is explained and tested at the hand of a synthetic polyphonic signal. The system produced usable transcriptions of real monophonic input signals to scores with standard notational symbols. The success of the system (as are the successes of all published polyphonic transcription systems) was limited for real polyphonic music signals. Nonetheless, the initial results are encouraging and indicate that the current implementation can serve as a platform for a more sophisticated and accurate system. / AFRIKAANSE OPSOMMING: In 'n baanbrekersprojek vir die Universiteit van Stellenbosch (en die breër Suid-Afrika) is 'n outomatiese musiek transkripsie stelselontwerp om die onderliggende teorie, konsepte en problematiek van polifoniese musiek transkripsie te ondersoek. Outomatiese musiek transkripsie kombineer kennis uit die navorsingsvelde van akoestiek, musiekteorie, syferseinverwerking en informasieteorie. Die sluitelkonsepte van elkeen van hierdie velde word kortliks weergegee soos dit van toepassing is op transkripsie stelsels. 'n Transkripsie stelsel met modules vir FFT-gebaseerde afskatting van polifoniese toonhoogtes, basiese naverwerking, afskatting van die graad van polifonie, bepaling van die sleutel, nootlengte kwantisering en bladmusiek notasie word aansluitend ontwikkel. Die werkswyse van die stelsel word aan hand van 'n sintetiese polifoniese sein verduidelik en getoets. Die stelsel lewer bruikbare transkripsies van enkelstemmige intreeseine na bladmusiek met standaard musieksimbole. Die sukses van die stelsel is beperk vir polifoniese musiek, soos ook die algemene geval is vir ander gepubliseerde meerstemmige transkripsie stelsels. Tog is die aanvanklike resultate belowend, met aanduidings dat die huidige implementering kan dien as 'n beginpunt vir die ontwikkeling van 'n meer gesofistikeerde en akkurate stelsel.

Thesis (MEng)--Stellenbosch University, 2004. / ENGLISH ABSTRACT: This thesis presents the design of a DSP based controller system for an auxiliary converter for generic energy storage connection to a line-interactive power compensator. The aim is to utilize a wide range of energy storage systems and incorporate them into the existing power compensator. This was done by adding a second converter to the system. The new controller was developed to control this converter and thereby the energy storage. A study was done on lead acid batteries, flow batteries and flywheels in order to gain a basic understanding of these systems and identify the requirements for their control. Based on these findings, a new DSP based controller and measuring system was developed. To test the new system a dc to dc converter was implemented for the control of lead acid and flow batteries. A dc to ac converter was also tested for the control of flywheel energy storage. / AFRIKAANSE OPSOMMING: Die tesis handeloor die ontwerp van'n DSP gebaseerde beheerstelsel vir 'n Iyninteraktiewe on-onderbreekbare kragbron met drywings-kompensasie met 'n hulp omsetter vir algemene enegiestoor koppeling. The doel is om 'n wye verskeindheid energie store in die huidige drywings elektroniese stelsel te inkorporeer. 'n Tweede omstetter is by die stelsel gevoeg om die energie stelsel te beheer. 'n Nuwe beheerder is ontwikkel om die omsetter te beheer en daardeur die energie stoor. Loodsuur batterye, vloei batterye en vliegwiele is ondersoek om 'n basiese begrip te vorm en te identifiseer wat nodig is vir die beheer van sulke energie store. Die nuwe DSP beheerder en meetstelsel is ontwikkel gebaseer op hierde ondervindings. Om die nuwe beheerstelsel te toets is 'n gs na gs omsetter geïmplementeer vir die beheer van loodsuur en floei batterye. Die omsetter is geherkonfigureer na 'n gs na ws opstelling en getoets. Die konfigurasie word gebruik vir die beheer van vliegwiele.

In this thesis we describe a method of mapping one-dimensional and multidimensional filter algorithms onto systolic architectures using the z-domain approach. In this approach the filter algorithm is first transformed into its corresponding z-domain equivalent and recursive expressions similar to single assignment codes are derived using Horner's rule or other polynomial evaluation techniques. By obtaining different recursive expressions, different systolic structures can be derived. The characteristics of these structures can easily be deduced from the recursive expressions. The multidimensional filters derived are modular and hierarchical, i.e., the three-dimensional structures are obtained from the two-dimensional ones which are in turn obtained from one-dimensional structures. In considering the design of any array processor, it is important to consider the design of the processing elements involved. The most important and demanding operation in these elements is the multiplication. Four different multipliers are designed in which the number of operations required to produce the desired result is reduced. The reduced number of operations along with the advantages of very-large-scale integration technology in terms of increased device density and faster switching make these multipliers potential candidates in high-speed signal processing applications. The first multiplier is an area-efficient multiplier that uses approximately 50% of the area of a full parallel multiplier. In this multiplier only the units yielding the most significant part of the product are used. In addition, a correction unit is incorporated to minimize the error resulting from circumventing the use of units yielding the least significant part of the product. The second multiplier is based on the modified octal Booth algorithm in which four-bit segments of the multiplier are scanned and corresponding operations effected on the multiplicand. The third multiplier is a diminished-1 multiplier that finds application in the Fermat number-theoretic transform. In this multiplier the use of a translator is circumvented and a novel technique for translation is incorporated in the multiplier structure. The fourth multiplier is one that performs an inner-product operation without the use of an accumulator thereby resulting in increased speed and reduced area. Finally we discuss the VLSI implementations of three of the multipliers mentioned above, a second-order digital filter, and a single processing element that can be used as a basic unit in designing one-dimensional and multidimensional digital filters. Some associated problems in digital-filter structure. viz., the quantization and overflow limit-cycle oscillations; have been taken into consideration and ways have been suggested for their elimination. / Graduate

Orientadores: Amauri Lopes, Jayme Garcia Arnal Barbedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-16T06:17:57Z (GMT). No. of bitstreams: 1 Tavares_TiagoFernandes_M.pdf: 763143 bytes, checksum: cfba6871d2749e15550eaebf61615c90 (MD5) Previous issue date: 2010 / Resumo: Este trabalho aborda o problema da transcrição automática de música aplicado à transcrição do baixo em músicas populares. Conceitos teóricos básicos em música e acústica são apresentados. Um método de transcrição existente na literatura científica é descrito e implementado. Na tentativa de melhorar a resolução das analises realizadas no domínio da freqüência, são utilizadas técnicas de predição linear. Verifica-se que o uso de tais técnicas traz ganhos consideráveis ao desempenho do transcritor automático implementado / Abstract: In this work, the problem of automatic transcription of the bass in popular music is studied. Basic theoretical concepts are presented. An automatic transcription method, obtained in scientific literature, is described and implemented. In order to improve the resolution of necessary frequency domain analysis, linear prediction techniques are used. It is observed that the use of such techniques brings sensible improvements to the accuracy of the implemented transcriptor / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Orientador: Hans Ingo Weber / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecanica / Made available in DSpace on 2018-07-21T16:53:45Z (GMT). No. of bitstreams: 1 Moraes_FranciscoJoseVicentede_M.pdf: 6703520 bytes, checksum: aa677f747599094668ea06d0f7536ad9 (MD5) Previous issue date: 1996 / Resumo: O conhecimento do comportamento dinâmico de equipamentos é importante, seja para o desenvolvimento e otimização de projetos ou para o monitoramento e diagnóstico de falhas de operação. Técnicas de processamento para extrair dos complicados sinais de vibrações mecânicas as informações pertinentes a cada análise têm sido investigadas. A análise de Fourier é capaz de revelar o conteúdo frequencial dos sinais. Porém. tal técnica é limitada à análise de sinais estacionários, já que os resultados obtidos são médias dentro do período amostrado, não distinguindo o instante de tempo em que um determinado evento ocorreu. Atualmente, cresce o interesse por sinais não estacionários, complexos. Em sua estrutura mas muito ricos em informações. Ateoria wavelet, capaz de fornecer informações locais de um sinal, é o objeto do presente estudo. A técnica consiste na decomposição do sinal em ondículas (wavelets) que, além de estarem relacionadas a um conteúdo frequencial. possuem um caráter localizado na linha do tempo. Assim, partindo da análise de Fourier, introduzimos os conceitos dessa nova técnica, bem como alguns exemplos práticos de aplicação / Abstract: The knowledge of the dynamic behaviour of machinery is important to develop modern design and condition monitoring. Thus, it is necessary to adequate appropriate processing methods in order to extract the desired informations from the complicated time domain mechanical vibration signals. The Fourier analysis has been extensively used to extract the frequency content from the signals. However, such technique is suitable only for stationary signals, since the given results correspond to average values on the sample period and do not discern the time location of discrete events. Nowadays, there has been a special interest on non-stationary signals, which have a complex structure but are very rich in informations about the real nature of the system. The wavelet theory, which is able to give local properties of a signal, is the subject of this workpiece. The technique consists on decomposing the given signal on small waves (wavelets), which are localised in both time and frequency domains. In the light of Fourier analysis, we introduce the bases of wavelet theory and some practical insights / Mestrado / Mecanica dos Sólidos e Projeto Mecanico / Mestre em Engenharia Mecânica