Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Cressler, John D.; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen; Committee Member: Shen, Shyh-Chiang; Committee Member: Zhou, Hao Min.

Thesis (Ph.D.) - Carleton University, 2007. / Includes bibliographical references (p. 194-201). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 82-92). Also available in electronic format on the Internet.

Typescript. Includes bibliographical references.

Thesis (doctoral)--VTT Micronova, 2006. / Includes bibliographical references. Also available on the World Wide Web.

Orientador: Maria Glória Caño de Andrade / Resumo: Este trabalho é baseado no estudo do comportamento de um diodo PIN de multicamadas utilizado como célula solar. Esse estudo é desenvolvido por meio de simulações em ambiente virtual, validada a partir de dados experimentais, e tem como foco principal o comportamento da geração de corrente pelo dispositivo, tanto na interação entre o dispositivo e uma determinada faixa do espectro luminoso, como na influência que as alterações nas dimensões dessa célula solar podem trazer na tensão gerada. O diodo PIN proposto encontra-se em uma lâmina SOI (Silicon On Insulator) com uma potencial aplicação destinada para a alimentação de circuitos que necessitam de ultrabaixa potência (ULP – Ultra Low Power), tais como sensores de campo para monitoramento e circuitos subcutâneos para monitoramento médico. É construído por uma camada dupla com diferentes semicondutores (silício e germânio) e, através de alterações em sua estrutura (mudança dos materiais e das dimensões), será verificado o comportamento dos principais parâmetros de uma célula solar, tais como fator de forma (FF), corrente fotogerada, tensão de circuito aberto, corrente de curto-circuito, tensão e corrente de trabalho e potência gerada pelo dispositivo. Adicionalmente, é também analisado o comportamento de penetração e absorção do espectro luminoso na célula solar e a existência de alterações nos parâmetros medidos quando há alteração na posição das camadas de semicondutores, com a finalidade de demonstrar que o incremento de uma... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: This work is based on the study of multilayer PIN diode used as a solar cell. This study was developed through simulations in a virtual environment with the main focus of the generation current by the device so much in the interaction between the device and a range of the light spectrum as well as in the influence the changes in the dimensions of the solar cell may bring in the voltage generated. It is composed of a double layer with different semiconductors (silicon and germanium), and though changes in its structure (materials and dimensions change), it will be verified the behavior of main parameters of a solar cell, such as Fill Factor (FF), photogenerated current, open-circuit voltage, short circuit current, work voltage and work current and the generated power will by the device. Additionally, it was also verified the behavior of the penetration and absorption of the light spectrum in the solar cell, and the existence of changes in the measured parameters when there is a change of position in the semiconductor layers, to demonstrate that the increase of a germanium layer may bring to the device concerning entirely silicon device. The results obtained indicate that there was an increase in the photogeneration when the germanium layer is positioned above the silicon layer. This way, this work demonstrates that small changes in the construction and the thickness of the lateral PIN diode used as a solar cell provide an increase in efficiency of more than 136% when comparing... (Complete abstract click electronic access below) / Mestre

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Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 110-113). Also available in electronic format on the Internet.

The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.