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Important characteristic of any VLSI design circuit is its power reliability, high operating speed and low silicon area implementation. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. The use of pipelines can also provide high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increases the area of implementation and restricts the maximum achievable frequency due to their delays. Memoryless pipelines based on dynamic design address these issues but, still requires high power consumption for the clock signal. In this thesis we present a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area over head and operating speed.

Certain single input, linearised extremum controllers of the empirical type described in the literature have been designed and their performances have been compared to that of an approximately optimal controller. The plant is subject to disturbances, lags and measurement noise. A dimensionless performance criterion and description of the plant have been used to present the results. A design procedure for a sinusoidal perturbation controller in connection with the above plant has been obtained, using a linear equivalent circuit for the system together with an experimentally obtained estimate of the equivalent circuit validity. Experimental results have shown that the resulting design is the best, and that the system is likely to remain stable, when the performance of the system is limited mainly by the measurement noise. This empirical controller has been compared with Roberts approximately optimal controller and has been shown to perform equally well if the effect of the lag is small. The performances of three different types of extremum controller have been compared when the plant lags can be neglected. The three controllers use sine wave perturbation, square wave perturbation, and square wave perturbation with a sample and hold unit in the controller. It has been shown that all three the perturbation frequency is infinite. When the perturbation frequency is limited, as in a practical system, the controllers without the sample and hold unit give better performance, at the expense of requiring the adjustment of an additional controller parameter.

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We consider the problem of maximum likelihood estimation of logistic sinusoidal regression models and develop some asymptotic theory including the consistency and joint rates of convergence for the maximum likelihood estimators. The key techniques build upon a synthesis of the results of Walker and Song and Li for the widely studied sinusoidal regression model and on making a connection to a result of Radchenko. Monte Carlo simulations are also presented to demonstrate the finite-sample performance of the estimators

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later.

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[pt] Trata-se de uma proposta que visa orientar o professor de Matemática do Ensino Médio em relação às dificuldades encontradas no ensino-aprendizagem da Trigonometria. Mais especificamente, para facilitar, com demonstrações alternativas, o desenvolvimento das fórmulas de adição de arcos. Para o desenvolvimento desse trabalho, optou-se pela metodologia da pesquisa documental, na qual se buscou os subsídios para o desenvolvimento da proposta. / [en] It is a proposal which aims to guide Mathematics High School teachers to cope with the difficulties faced in the teaching-learning process of trigonometry. More specifically, it will facilitate the development of arc addition formulas by the use of alternative statements. In order to improve this work, it was chosen the documentary research methodology, where the subsidies for the development of this proposal were searched.

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This thesis performs a quantitative study, derived from the Neyman-Pearson framework, on the robustness of the matched filter detector corrupted by zero mean, independent and identically distributed white Gaussian noise. The variance of the noise is assumed to be imperfectly known, but some knowledge about a nominal value is presumed. We utilized slope as a unit to quantify the robustness for different signal strengths, nominals, and sample sizes. Following to this, a weighting method is applied to the slope range of interest, the so called tolerable range, as to analyze the likelihood of these extreme slopes to occur. A ratio of the first and last quarter section of the tolerable range have been taken in order to obtain the likelihood ratio for the low slopes to occur. We finalized our analysis by developing a method that quantifies confidence as a measure of robustness. Both weighted and non-weighted procedures were applied over the tolerable range, where the weighted procedure puts greater emphasis on values near the nominal. The quantitative analysis results show the detector to be non-robust and deliver poor performance for low signal-to-noise ratios. For moderate signal strengths, the detector performs rather well if the nominal and sample size are chosen wisely. The detector has great performance and robustness for high signal-to-noise ratios. This even remains true when only a few samples are taken or when the practitioner is uncertain about the nominal chosen.