Made available in DSpace on 2014-06-12T15:58:18Z (GMT). No. of bitstreams: 2 arquivo3452_1.pdf: 3452194 bytes, checksum: f140ad60d48eddac72b254cec44bfe46 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2011 / O advento das novas tecnologias Very Large Scale Integration (VLSI) e o crescimento da demanda por produtos eletrônicos no mundo estão trazendo um aumento explosivo na complexidade dos circuitos eletrônicos. A contrario sensu, o tempo de mercado (time-tomarket) de um produto eletrônico, e o tempo de projeto necessário para produção e venda de um sistema estão ficando cada vez menores. Para que o circuito integrado chegue ao mercado com o funcionamento esperado é necessário realizar testes. Parte desses testes é chamada de verificação funcional e é a parte do projeto que requer mais tempo de desenvolvimento. Buscam-se sempre novos métodos que permitam que a verificação funcional seja realizada de forma ágil, fácil e que proveja uma maior reusabilidade e diminuição da complexidade na construção do ambiente de simulação, sem interferir negativamente na qualidade do processo de verificação e do produto. Dessa forma, o uso de uma metodologia de verificação funcional eficiente e de ferramentas que auxiliem o engenheiro de verificação funcional é de grande valia. A metodologia OVM_tpi permite o desenvolvimento de todo o fluxo de construção de um ambiente de verificação, independente da escolha feita pela equipe desenvolvedora, de forma que o ambiente de simulação seja gerado antes da implementação do circuito a ser verificado (Design Under Verification - DUV). Além disso, ataca os principais desafios do processo de verificação funcional, tempo e custo de desenvolvimento, contribuindo para uma diminuição da complexidade, reusabilidade, comunicação entre o ambiente com uma interface bem definida e diminuição no tempo de desenvolvimento de um testbench através do uso de templates que criam de forma semiautomática partes do ambiente de verificação. OVM_tpi teve como principal base a metodologia Open Verification Methodology (OVM), utilizando sua biblioteca para a construção do testbench e o paradigma de linguagem orientação objeto suportado por SystemVerilog, linguagem criada especialmente para verificação funcional e design. Sua validação foi através de estudos de casos que demonstraram a eficácia do seu uso, tanto para circuitos unidirecionais, quanto para bidirecionais

Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

Magíster en Ciencias de la Ingeniería, Mención Eléctrica / Ingeniero Civil Electricista / Esta tesis se centra en el estudio del estado de carga (SoC: state of charge) para acumuladores de energía del tipo plomo ácido. Este parámetro es de suma importancia en aplicaciones donde el acumulador está sometido permanentemente a situaciones de carga y/o descarga, como las que se presentan en vehículos eléctricos o micro-redes, por ejemplo. El SoC se define como la energía expresada como un porcentaje de la capacidad nominal, que aún está disponible para ser utilizada. Este indicador depende de muchas otras magnitudes, tales como: temperatura, tasas de corriente de carga/descarga, tiempo de uso, histéresis, y auto descarga. Este parámetro no es medible, por lo cual es necesario estimarlo en base a mediciones de otras señales disponibles en los acumuladores, tales como tensión, corriente y temperatura. Para desarrollar un estimador del SoC hay que tener en cuenta dos aspectos; el primero de ellos es contar con un buen modelo que represente el comportamiento del acumulador de manera adecuada, mientras que el segundo, dice relación con el algoritmo utilizado para realizar la estimación. Ambos aspectos suponen contar con información del acumulador para poder identificar el modelo y diseñar el estimador. Por lo tanto, se establecieron los objetivos de la tesis, los cuales corresponden en primer término a la construcción de un prototipo con el cual se pueda someter el banco de acumuladores a diversos perfiles de carga/descarga. Luego en base a la información generada mediante este sistema experimental, derivar un modelo de baterías que sea sencillo de implementar y requiera poca cantidad de información. Dicho modelo corresponde a un modelo difuso. Con el modelo de baterías ya definido, se utiliza el algoritmo del filtro extendido de Kalman para desarrollar un estimador del SoC basado en el modelo propuesto. Es importante destacar que tanto el modelo como el estimador son evaluados y comparados con modelos de baterías convencionales y con estimadores basados en ellos. (Implementados con el algoritmo de Kalman). Los aportes del trabajo de tesis, son en primer lugar, la construcción del sistema experimental, el cual servirá para otras investigaciones relacionadas a acumuladores de energía. En segundo término, se tiene que la metodología basada en lógica difusa (para el desarrollo del modelo), es novedosa, pues hasta el momento sólo ha sido implementada con datos basados en mediciones en el dominio de la frecuencia o en conjunto con redes neuronales. Lo que supone en el primer caso que el modelo no pueda ser llevado a la práctica debido al costoso equipamiento necesario para obtener datos en el dominio de la frecuencia, y en la necesidad de contar con gran cantidad de información para el segundo caso. Finalmente es importante mencionar que las baterías consideradas para esta tesis, están presentes en la micro-red Huatacondo perteneciente al Centro de Energía de la Universidad de Chile.

Modern consumer electronic systems are mostly based on analog and digital circuits and are designed as analog/mixed-signal systems on chip (AMS-SoCs). the integration of analog and digital circuits on the same die makes the system cost effective. in AMS-SoCs, analog and mixed-signal portions have not traditionally received much attention due to their complexity. As the fabrication technology advances, the simulation times for AMS-SoC circuits become more complex and take significant amounts of time. the time allocated for the circuit design and optimization creates a need to reduce the simulation time. the time constraints placed on designers are imposed by the ever-shortening time to market and non-recurrent cost of the chip. This dissertation proposes the use of a novel method, called metamodeling, and intelligent optimization algorithms to reduce the design time. Metamodel-based ultra-fast design flows are proposed and investigated. Metamodel creation is a one time process and relies on fast sampling through accurate parasitic-aware simulations. One of the targets of this dissertation is to minimize the sample size while retaining the accuracy of the model. in order to achieve this goal, different statistical sampling techniques are explored and applied to various AMS-SoC circuits. Also, different metamodel functions are explored for their accuracy and application to AMS-SoCs. Several different optimization algorithms are compared for global optimization accuracy and convergence. Three different AMS circuits, ring oscillator, inductor-capacitor voltage-controlled oscillator (LC-VCO) and phase locked loop (PLL) that are present in many AMS-SoC are used in this study for design flow application. Metamodels created in this dissertation provide accuracy with an error of less than 2% from the physical layout simulations. After optimal sampling investigation, metamodel functions and optimization algorithms are ranked in terms of speed and accuracy. Experimental results show that the proposed design flow provides roughly 5,000x speedup over conventional design flows. Thus, this dissertation greatly advances the state-of-the-art in mixed-signal design and will assist towards making consumer electronics cheaper and affordable.

A behavioral battery modeling approach aimed at large format batteries is the topic of this dissertation. Drawing from the development of cell - level electrical analogue battery models, the comprehensive modeling approach described here shows how to scale a high fidelity battery cell model to a computationally fast battery model of large format batteries for system level design and simulation. The accurate behavioral battery model is performance - driven and tailored for stringent system simulation requirements. A novel bandwidth - based parameter extraction algorithm and advanced State of Charge (SOC) - Open Circuit Voltage (OCV) profile identification method are presented. While a real-world battery system is non-linear and time varying, a truncated representation of the system is provided by a commonly studied non-physical "electrical analogue" battery model. However, the limited bandwidth characteristic of the electrical analogue battery model is often overlooked. The reported algorithm starts by assessing a desired battery application, followed by modeling the battery according to the application bandwidth, and then estimating the model parameters using the sequential quadratic programming method. This approach recognizes and makes use of the limited bandwidth of the battery model by reconciling the bandwidth of the application into the bandwidth of the electrical analogue battery model. The model will help in vehicle concept development, and provide an analytical tool during the process of selecting the most appropriate battery during system design but before a prototype system is built. Another application is to represent the plant in realtime model-based battery management and control systems embedded in actual application controllers. This modeling approach is independent of the battery chemistry and therefore it is applicable to lithium-ion, nickel-metal-hydride (NiMH), and lead-acid batteries, among others.

No description available.

En los últimos años dispositivos móviles y sistemas de cómputo han logrado disminuir sus tamaños y aumentar su funcionalidad sin sacrificar sus consumos energéticos a través de buenas estrategias de administración de energía. En esta tesis se aborda la implementación de convertidores de potencia para administración de energía. Dos líneas de investigación serán abordadas; la primera a nivel de sistemas empaquetados (system in a package) y la segunda en sistemas en circuitos integrados (system on chip). En la primera parte se presenta un análisis de la técnica de desvío de ondulación (ripple steering) aplicada a tecnologías de cerámicas de baja temperatura de sinterizado (low temperature co-fired ceramics, LTCC) magnético y se analiza la factibilidad de usarla en filtros de potencia. Luego se determina la zona de trabajo en la que el filtro con ripple steering presenta mayor atenuación que un filtro LC de 2do orden con el mismo volumen. Para esto se modela el comportamiento del filtro dependiendo de diferentes parámetros de fabricación y se propone una figura de mérito que evalúa la mejora en la atenuación entre el fltro con ripple steering y el filtro clásico LC de 2do orden con el mismo volumen. Para validar el modelo propuesto y la figura de mérito se construyen inductores acoplados en LTCC que son utilizados en un filtro de potencia. Los resultados experimentales muestran que el filtro con ripple steering se desempeña mejor, con una atenuación 66% más alta que el filtro clásico LC de 2do orden. Ambos filtros son luego utilizados como filtros de salida de un convertidor reductor (buck) y se comprueba que la ondulación de salida (ripple) también es 66% menor para el filtro con ripple steering. En la segunda parte de la tesis se aborda el caso de estudio de un convertidor de múltiples salidas utilizando una única inductancia (single inductor multiple outputs, SIMO) completamente integrado, orientado a la administración de energía dentro de la misma pastilla de silicio (die) de un sistema en circuito integrado. El convertidor posee dos salidas, una reductora (buck) y otra elevadora (boost) de tensión. Para llevar a cabo la implementación se elije una tecnología CMOS de 65 nm, ampliamente utilizada en sistemas en circuitos integrados. Se propone y desarrolla una estrategia de control por histéresis, los módulos y circuitos necesarios para su implementación. Comparadores de alta velocidad, transductores de corriente instantánea y media y los sensores de corriente cero por la inductancia son desarrollados junto con una máquina de estados asincrónica que ofrece las mejores características para el control del sistema. El convertidor desarrollado genera tensiones de 1.2 V y 0.8 V a partir de una tensión de 1 V. Las salidas poseen una regulación del 10% en la condición de máxima carga que es de 50 mA. El convertidor logra un pico de eficiencia mayor al 70 %, que es comparable a la eficiencia reportada en trabajos previos y superior a la que se puede obtener con reguladores lineales. / In recent years, mobile devices and computer systems have reduced their size and increased functionality without increasing their energy consumption through good energy management strategies. In this thesis the implementation of power converters is discussed for power management. Two lines of research will be addressed; the first in system in a package and the second in system on chip. In the first part, an analysis of the ripple steering technique applied to magnetic low temperature co-fired ceramics (LTCC) and the feasibility to be applied to power filters are presented. The working zone where the filter with ripple steering shows a greater attenuation than a LC filter of 2nd order with the same volume is determined. With this purpose, the filter behavior is modeled depending on various manufacturing parameters and a figure of merit which evaluates the improvement in attenuation between the filter with ripple steering and classical LC filter 2nd order with the same volume is proposed. To validate the proposed model and the figure of merit LTCC coupled inductors which are used in a power filter are constructed. Experimental results show that the filter with ripple steering performs better than the classic LC filter 2nd order with an attenuation 66% higher. Both filters are then used as output filters of a buck converter and it can be checked that the output ripple is 66% lower for the filter with ripple steering. In the second part of the thesis the case study of a converter with multiple outputs using a single inductor (SIMO) fully integrated, oriented power management within the same die of a system integrated circuit. The inverter has two outputs, a buck-like and a boost-like. To carry out the implementation, 65 nm CMOS technology is chosen since it is widely used in system on a chip. A hysteretic control strategy is proposed and developed; modules and circuits necessary for its implementation are also carried on. High speed comparators, instantaneous, average and zero inductor current transducers and sensors are developed together with an asynchronous state machine which offers the best features for control the system. The developed converter generates output voltages of 1.2 V and 0.8 V from a input voltage of 1 V. The outputs have a regulation of 10% at maximum load condition (50 mA). The converter achieves a peak eficiency of 70 %, which is better than the expected eficiency of a linear regulator and it is comparable with the fully integrated power converter eficiency previously reported in the literature.

Abstrakt Bakgrund: Antonovskys sense of coherence (SOC)/känsla av sammanhang (KASAM) är ett globalt använt begrepp. Mätverktyget SOC-skalan som förekommer i minst 15 olika versioner används inom många olika vetenskapliga studier. Syftet med denna litteraturöversikt är att beskriva vilka perspektiv och huvudsakliga resultat som lyfts fram i samtida svensk vetenskaplig forskning kring stress som använder SOC-begreppet och SOC-skalan. Metod: Text- och innehållsanalys av forskningsfokus och perspektiv i de senaste fem årens vetenskapliga studier kring stress och sense of coherence i Sverige. Resultat: SOC-skalan används i studier med olika design inom många olika forskningsområden. Dominerande perspektiv i samtida svensk forskning med SOC-skalan som huvudsakligt eller kompletterande verktyg är det holistiska perspektivet, individperspektivet, genusperspektivet samt föräldraperspektivet. Diskussion: SOC-skalans vetenskapliga användning speglar dagens svenska samhälls- och diskussionsklimat. SOC-skalans validitet och reliabilitet förblir föremål för diskussion, då olika versioner av SOC-skalan ger olika resultat och olika möjligheter till analys. / Abstract Background: Antonovsky’s sense of coherence (SOC) is a globally used concept. The SOC scale tool exists in at least 15 different versions and is used in many different scientific studies. The aim of this literature review is to describe which perspectives and main results are highlighted in contemporary Swedish research concerning stress that uses the SOC concept and the SOC scale. Method: Text and content analysis concerning research focus and perspectives in scientific studies concerning stress and sense of coherence in Sweden in the last five years. Results: The SOC scale is used in studies of different designs within many different fields of research. Dominating perspectives in contemporary Swedish research using the SOC scale as a main or complementary tool are the holistic perspective, the individual perspective, the gender perspective and the parental perspective. Discussion: The scientific use of the SOC scale reflects the social discussion climate in Sweden of today. The validity and reliability of the SOC scale remain subjects of discussion, as different versions of the SOC scale give different results and different analyzing possibilities.

La problématique de cette thèse se tient à l'interface des domaines scientifiques de l'adéquation algorithme architecture, des systèmes de vision bio-inspirée en robotique mobile et du traitement d'images.Le but est de rendre un robot autonome dans son processus de perception visuelle, en intégrant au sein du robot cette tâche cognitive habituellement déportée sur un serveur de calcul distant.Pour atteindre cet objectif, l'approche de conception employée suit un processus d'adéquation algorithme architecture, où les différentes étapes de traitement d'images sont analysées minutieusement.Les traitements d'image sont modifiés et déployés sur une architecture embarquée de façon à respecter des contraintes d'exécution temps-réel imposées par le contexte robotique.La robotique mobile est un sujet de recherche académique qui s'appuie sur des approches bio-mimétiques.La vision artificielle étudiée dans notre contexte emploie une approche bio-inspirée multi-résolution, basée sur l'extraction et la mise en forme de zones caractéristiques de l'image.Du fait de la complexité de ces traitements et des nombreuses contraintes liées à l'autonomie du robot, le déploiement de ce système de vision nécessite une démarche rigoureuse et complète d'exploration architecturale logicielle et matérielle.Ce processus d'exploration de l'espace de conception est présenté dans cette thèse.Les résultats de cette exploration ont mené à la conception d'une architecture principalement composée d'accélérateurs matériels de traitements (IP) paramétrables et modulaires, qui sera déployée sur un circuit reconfigurable de type FPGA.Ces IP et le fonctionnement interne de chacun d'entre eux sont décrits dans le document.L'impact des paramètres architecturaux sur l'utilisation des ressources matérielles est étudié pour les traitements principaux.Le déploiement de la partie logicielle restante est présenté pour plusieurs plate-formes FPGA potentielles.Les performances obtenues pour cette solution architecturale sont enfin présentées.Ces résultats nous permettent aujourd'hui de conclure que la solution proposée permet d'embarquer le système de vision dans des robots mobiles en respectant les contraintes temps-réel imposées. / This Ph.D Thesis stands at the crossroads of three scientific domains : algorithm-architecture adequacy, bio-inspired vision systems in mobile robotics, and image processing.The goal is to make a robot autonomous in its visual perception, by the integration to the robot of this cognitive task, usually executed on remote processing servers.To achieve this goal, the design approach follows a path of algorithm architecture adequacy, where the different image processing steps of the vision system are minutely analysed.The image processing tasks are adapted and implemented on an embedded architecture in order to respect the real-time constraints imposed by the robotic context.Mobile robotics as an academic research topic based on bio-mimetism.The artificial vision system studied in our context uses a bio-inspired multi-resolution approach, based on the extraction and formatting of interest zones of the image.Because of the complexity of these tasks and the many constraints due to the autonomy of the robot, the implementation of this vision system requires a rigorous and complete procedure for the software and hardware architectural exploration.This processus of exploration of the design space is presented in this document.The results of this exploration have led to the design of an architecture primarly based on parametrable and scalable dedicated hardware processing units (IPs), which will be implemented on an FPGA reconfigurable circuit.These IPs and the inner workings of each of them are described in the document.The impact of their architectural parameters on the FPGA resources is studied for the main processing units.The implementation of the software part is presented for several potential FPGA platforms.The achieved performance for this architectural solution are finally presented.These results allow us to conclude that the proposed solution allows the vision system to be embedded in mobile robots within the imposed real-time constraints.

MPSoCs (systèmes multiprocesseurs sur puces) avec des centaines de cœurs sont déjà disponibles sur le marché. Selon le ITRS, ces systèmes intégreront des milliers de cœurs à la fin de la décennie. La définition du cœur, où chaque tâche sera exécutée dans le système, est une question majeure dans la conception de MPSoCs. Dans la littérature, cette question est définie comme allocation de tâches. La croissance du nombre de cœurs augmente la complexité de l'allocation de tâches. Les principales préoccupations en matière d'allocation de tâches dans des grands MPSoCs incluent: (i) l'évolutivité; (ii) la charge de travail dynamique; et (iii) la fiabilité. Il est nécessaire de distribuer la décision d'allocation de tâches à travers le système afin d'assurer l'évolutivité. La charge de travail de grands MPSoCs peut être dynamique, à savoir, de nouvelles applications peuvent commencer à tout moment, conduisant à différents scénarios d'allocation. Par conséquent, il est nécessaire d'exécuter le processus d'allocation à l'exécution pour soutenir une charge de travail dynamique. La fiabilité est étroitement liée à la distribution de la charge de travail du système. Un déséquilibre de charge peut générer des hotspots et autres implications thermiques, ce qui peut entraîner un fonctionnement peu fiable du système. Dans de grands MPSoCs, les problèmes de fiabilité empirent puisque l'augmentation du nombre de cœurs sur la même puce augmente la densité de puissance et, par conséquent, la température du système. La littérature présente différentes techniques d'allocation de tâches pour améliorer la fiabilité du système. Cependant, ces techniques utilisent des approches d'allocation centralisées, qui ne sont pas évolutives. Pour répondre à ces trois défis, l'objectif principal de cette Thèse est de proposer et évaluer des heuristiques d'allocation de tâches distribuées et dynamiques en assurant l'évolutivité et une distribution équitable de la charge de travail. Une distribution équitable de la charge de travail et du trafic du NoC (réseau sur puce) augmente la fiabilité du système dans le long terme, en raison de la minimisation des régions de hotspot. Pour permettre l'exploration de l'espace de conception de grands MPSoCs, la première contribution de cette Thèse se situe dans le cadre d'une modélisation multi-niveaux, qui prend en compte différents modèles et de capacités de débogage qui enrichissent et facilitent la conception des MPSoCs. La simulation de modèles de niveau inférieur (par exemple RTL) génère des paramètres de performance utilisés pour calibrer des modèles abstraits (sans précision d'horloge). Les modèles abstraits permettent d'explorer des heuristiques d'allocation de tâches dans de grands systèmes. La plupart des techniques d'allocation de tâches se focalisent sur l'optimisation du volume de communication, ce qui peut compromettre la fiabilité du système, en raison d'une surcharge des processeurs. D'autre part, une heuristique qui optimise seulement la distribution de la charge de travail peut surcharger le NoC et compromettre sa fiabilité. La deuxième contribution importante de cette Thèse est la proposition d'heuristiques d'allocation de tâches dynamiques et distribuées, qui réalisent un compromis entre le volume de communication (liens du NoC) et la distribution de la charge de travail (de l'utilisation des processeurs). Des résultats liés au temps d'exécution, au volume de la communication, à la consommation d'énergie, aux traces de puissance et à la distribution de la température dans les grands MPSoCs (144 processeurs) confirment l'hypothèse de compromis. Faire un compromis entre la réduction du volume de communication et une distribution équitable de la charge de travail améliore le système de manière fiable grâce à la réduction des régions de hotspots, sans compromettre la performance du système. / MPSoCs with hundreds of cores are already available in the market. According to the ITRS roadmap, such systems will integrate thousands of cores by the end of the decade. The definition of where each task will execute in the system is a major issue in the MPSoC design. In the literature, this issue is defined as task mapping. The growth in the number of cores increases the complexity of the task mapping. The main concerns in task mapping in large systems include: (i) scalability; (ii) dynamic workload; and (iii) reliability. It is necessary to distribute the mapping decision across the system to ensure scalability. The workload of emerging large MPSoCs may be dynamic, i.e., new applications may start at any moment, leading to different mapping scenarios. Therefore, it is necessary to execute the mapping process at runtime to support a dynamic workload. Reliability is tightly connected to the system workload distribution. Load imbalance may generate hotspots zones and consequently thermal implications, which may result in unreliable system operation. In large scale MPSoCs, reliability issues get worse since the growing number of cores on the same die increases power densities and, consequently, the system temperature. The literature presents different task mapping techniques to improve system reliability. However, such approaches use a centralized mapping approach, which are not scalable. To address these three challenges, the main goal of this Thesis is to propose and evaluate distributed mapping heuristics, executed at runtime, ensuring scalability and a fair workload distribution. Distributing the workload and the traffic inside the NoC increases the system reliability in long-term, due to the minimization of hotspot regions. To enable the design space exploration of large MPSoCs the first contribution of the Thesis lies in a multi-level modeling framework, which supports different models and debugging capabilities that enrich and facilitate the design of MPSoCs. The simulation of lower level models (e.g. RTL) generates performance parameters used to calibrate abstract models (e.g. untimed models). The abstract models pave the way to explore mapping heuristics in large systems. Most mapping techniques focus on optimizing communication volume in the NoC, which may compromise reliability due to overload processors. On the other hand, a heuristic optimizing only the workload distribution may overload NoC links, compromising its reliability. The second significant contribution of the Thesis is the proposition of dynamic and distributed mapping heuristics, making a tradeoff between communication volume (NoC links) and workload distribution (CPU usage). Results related to execution time, communication volume, energy consumption, power traces and temperature distribution in large MPSoCs (144 processors) confirm the tradeoff hypothesis. Trading off workload and communication volume improves system reliably through the reduction of hotspots regions, without compromising system performance.