International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / The MicroDAS-1000 is an airborne Data Acquisition System (DAS) designed to meet the growing needs of airframe manufacturers for extensive test data accumulation, processing and evaluation. As such, the system has been designed with emphasis on modularity, miniaturization and ease of operator usage and expansion. The MicroDAS product line includes a series of components used as building blocks to configure systems of virtually any size. The modular design of these components allows considerable latitude to the instrumentation engineer in configuring systems for simple or complex applications. The modular concept has been extended to the design of plug-in modules for different functional requirements and system applications. All units are under software control to allow rapid reconfiguration and setup as requirements for instrumentation and data gathering change.

We propose a model of an agent which is both logical and operational. Our model of vivid agents takes into account that agents need not only the ability to draw inferences but also to update their current knowledge state, to represent and to perform (and to simulate the execution of) actions in order to generate and exe- cute plans, and to react and interact in response to perception and communication events. We illustrate our formalization of this basic functionality of an agent by means of examples. We also show how our model fits into the transition system semantics of concurrent reactive systems by identifying the five basic transitions of vivid agent systems: perception, reaction, planning, action, and replanning.

Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.