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This thesis examines the high peak-to-average-power ratio (PAPR) problem of OFDM and other spectrally-efficient multicarrier modulation schemes, specifically their stringent requirements for highly linear, power-inefficient amplification. The thesis then presents a most intriguing answer to the PAPR-problem in the form of a constant-envelope OFDM (CE-OFDM) waveform, a waveform which employs phase modulation to transform the high-PAPR OFDM signal into a constant envelope signal, like FSK or GMSK, which can be amplified with non-linear power amplifiers at near saturation levels of efficiency. A brief analytical description of CE-OFDM and its suboptimal receiver architecture is provided in order to define and analyze the key parameters of the waveform and their performance impacts. The primary contribution of this thesis is a highly tunable software-defined radio (SDR) implementation of the waveform which enables rapid-prototyping and testing of CE-OFDM systems. The digital baseband processing of the waveform is executed on a general purpose processor (GPP) in the Linux Ubuntu 14.04 operating system, and programmed using the GNU Radio SDR software framework with a mixture of Python and C++ routines. A detailed description of the software implementation is provided, and baseband simulations of the SDR CE-OFDM receiver in additive white Gaussian noise (AWGN) validate the performance of the implemented signal processing. A fully-functional CE-OFDM radio system is proposed in which GPPs executing the software defined transmitter and receiver routines are interfaced with Ettus Universal Software Radio Peripheral (USRP) transceiver front ends. A software testbench is created to enable rapid configuration and testing of the CE-OFDM waveform over all permutations of its parameters, over both simulated and physical RF channels, to draw deeper insights into the characteristics of the waveform and the necessary design considerations and improvements for further development and deployment of CE-OFDM systems. / Master of Science

Radio technology is rapidly evolving and as processing capabilities and algorithms become more complex, the need for alternative compilation and user interface abstraction increases. Field Programmable Gate Array (FPGA) technology introduces unique reconfigurable hardware architectures that can aid in software defined radio (SDR) design. FPGAs have greater processing capability than traditional general purpose processors (GPP) found in desktop workstations. This work builds on an ongoing project, GReasy, that augments a Linux based open source SDR development platform, GNU Radio, with FPGA processing capabilities. By delegating processing intensive portions of a radio design to the Xilinx Zynq FPGA architecture, the domain of deployable radios by GNU Radio can be broadened. Xilinx Zynq, integrates the FPGA fabric and CPU onto a single chip, which eliminates the need for a controlling host computer; thus, providing a single, portable, low-power, embedded platform. This thesis presents a Zynq capable version of GNU Radio -- an open-source rapid radio deployment tool -- with an enhanced flow that utilizes the processing capability of FPGAs. This work features TFlow -- an FPGA back-end compilation accelerator for instant FPGA assembly. GReasy generates a description of the hardware components that are used by TFlow for the instant FPGA assembly. Once the FPGA is programmed with a design based on the description generated by GReasy, modules and the target hardware can be parameterized to realize an even larger class of applications and further solidify the concept of rapid assembly of software defined radios. / Master of Science

This thesis discusses the design of two Physical Layer Security (PLS) techniques on Software Defined Radios (SDRs). PLS is a classification of security methods that take advantage of physical properties in the waveform or channel to secure communication. These schemes can be used to directly obfuscate the signal from eavesdroppers, or even generate secret keys for traditional encryption methods. Over the past decade, advancements in Multiple-Input Multiple-Output systems have expanded the potential capabilities of PLS while the development of technologies such as the Internet of Things has provided new applications. As a result, this field has become heavily researched, but is still lacking implementations. The design work in this thesis attempts to alleviate this problem by establishing SDR designs geared towards Over-the-Air experimentation. The first design involves a 2x1 Multiple-Input Single-Output system where the transmitter uses Channel State Information from the intended receiver to inject Artificial Noise (AN) into the receiver's nullspace. The AN is consequently not seen by the intended receiver, however, it will interfere with eavesdroppers experiencing independent channel fading. The second design involves a single-carrier Alamouti coding system with pseudo-random phase shifts applied to each transmit antenna, referred to as Phase-Enciphered Alamouti Coding (PEAC). The intended receiver has knowledge of the pseudo-random sequence and can undo these phase shifts when performing the Alamouti equalization, while an eavesdropper without knowledge of the sequence will be unable to decode the signal. / Master of Science / This thesis discusses the design of two Physical Layer Security (PLS) techniques. PLS is a classification of wireless communication security methods that take advantage of physical properties in transmission or environment to secure communication. These schemes can be used to directly obfuscate the signal from eavesdroppers, or even generate secret keys for traditional encryption methods. Over the past decade, advancements in Multiple-Input Multiple-Output systems have expanded the potential capabilities of PLS while the development of technologies such as the Internet of Things has provided new applications. As a result, this field has become heavily researched, but is still lacking implementations. The design work in this thesis attempts to alleviate this problem by establishing systems that can be used for laboratory experimentation.

In this thesis, two different cases of hybrid IEEE 802.15.4 PHY (Physical Layer) implementation are explored. The first case is an FPGA implementation of IEEE 802.15.4 PHY on the Xilinx Spartan-3A DSP FPGA of USRP N210. All of the signal processing tasks are performed on the FPGA, while less complex MAC (Media Access Control) layer tasks are performed in GNU Radio on the host. The second case is an implementation of a multi-channel IEEE 802.15.4 receiver. A four-channel channelizer is implemented on the external Virtex 5 FPGA, while the IEEE 802.15.4 receiver is implemented in GNU Radio on the host. The first case demonstrates how spare resources in USRP's FPGA can be used to implement signal processing task while still interfacing with GNU Radio. The second case builds a platform on which a combination of GNU Radio and an external FPGA can be used for signal processing and USRP as an RF source. This thesis lays out the groundwork for more complex wireless protocols to be implemented on any combination of USRP's FPGA, an external FPGA, and GNU Radio. / Master of Science

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This thesis presents the digital design for an impulse-based ultra wideband communication system capable of supporting raw data rates of up to 100 MB/s. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non real-time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes. As proof-of-concept, a scaled down prototype receiver which utilized 2 ADCs and a Xilinx Virtex-II Pro (XC2VP30) FPGA was fabricated and tested. / Master of Science

The wireless market of the future will demand inexpensive hardware, expandability, interoperability, and the implementation of advanced signal processing functions--i.e. a software radio. Configurable computing machines are often ideal software radio platforms. In particular, the Stallion reconfigurable processor's efficient hardware reuse and scalability fulfill these radios' demands. The advantages of Stallion-based design inspired an FPGA-based software radio - the proto-Stallion receiver. This thesis introduces the proto-Stallion architecture and details its implementation on the SLAAC-1V FPGA platform. Although this thesis presents a specific radio implementation, this architecture is flexible; it can support a variety of applications within its fixed framework. This implemented single-user DS-CDMA receiver utilizes an LMS adaptive filter that can combat MAI and constructively combine multipath; most notably, this receiver employs an adaptive tracking algorithm that harnesses the LMS algorithm to maintain symbol synchronization. The proto-Stallion receiver demonstrates the dependence of adaptive tracking on channel noise; the algorithm requires significant noise levels to maintain synchronization. / Master of Science

The idea of wireless distributed computing (WDC) is rapidly gaining recognition owing to its promising potential in military, public safety and commercial applications. This concept basically entails distributing a computationally intensive task that one radio device is assigned, among its neighboring peer radio devices. The added processing power of multiple radios can be harnessed to significantly reduce the time consumed in obtaining the results of the original complex task. Since the idea of wireless distributed computing depends on a radio device forming a network with its peers, it is imperative and necessary to have a medium access control (MAC) protocol for such networks which is capable of scheduling channel access by multiple radios in the network, ensuring reliable data transfer, incorporating rate adaptation as well as handling link failures. The thesis presented here elaborates the design and implementation of such a MAC protocol for WDC employed in a practical network of radio devices configurable through software. It also brings to light the design and implementation constraints and challenges faced in this endeavor and puts forward viable solutions. / Master of Science

The rapidly developing wireless market has spawned a multitude of different standards for cellular, PCS, and wireless data. To allow users the ability to access services conforming to disparate standards, multimode handsets capable of software reconfiguration are needed. These "software radios" are distinguished from their traditional counterparts by their strong reliance on digital channel filtering and demodulation which may be reprogrammed to receive different standards. In these radios, higher dynamic range is required from the analog portion, most notably, the analog-to-digital converter (ADC). This research examines through analysis and simulation the performance requirements of analog-to-digital converters for use in radios which are conformant to the AMPS, IS-54, GSM, and IS-95 cellular standards. Simulations reveal the degradation in performance under conditions of off-channel interference, fading, and converter nonlinearities. Included in this analysis is the design of automatic gain control (AGC) for narrowband and IS-95 spread spectrum systems to optimize quantization noise and distortion due to A/D overload. Lastly, methods for improving the dynamic range of the analog-to-digital interface such as nonuniform quantization, companding, and dither are presented. The development of a novel A/D using a direct-sequence pseudo-noise (DSPN) technique in conjunction with an asymmetrical quantizer is presented and compared with standard dither techniques. Advantages of this technique compared to ordinary ADC's include an almost one bit improvement in resolution, quantization noise whitening, elimination of A/D offsets, and the ability to simultaneously digitize multiple analog signals with a single quantizer. The technique requires no synchronization and is easily implemented. / Master of Science