Within the context of the imminent implementation of the Pb-free soldering in Europe in 2006, this thesis addresses the gap in understanding that has emerged in the fundamental materials issues between well-understood and mature lead-containing solders and a plethora of new, Pb-free solders for which there are neither long term reliability data nor understanding of the materials behaviour and how these might be influenced by manufacture and in-service conditions. In addition, this thesis also addresses the question as to whether the solder joint size and geometry could become a reliability issue and therefore affect the implementation of the Pb-free solders in ultrafine micro joints. Thermodynamic calculations using MTDATA (developed by the National Physical Laboratory, NPL, UK) together with a thermodynamic database for solders under either equilibrium or Scheil conditions, have shown their usefulness in Pb-free solder design and processing, generating a wealth of information in respect of the temperature dependence of phase formation and composition. The predictions from MTDATA on a number of selected systems is generally in good agreement with the results from experimental work, and has assisted in the understanding of the microstructure and mechanical properties of the Pb-free solders and the implications of their interactions with a tin-lead solder. However, further critical assessment and the addition of new elements into the solder database, such as Ni and P, are required to make MTDA TA a more effective computational tool to assist the optimization of processing parameters and cost-effective production in using Pb-free solders. Molten solder can interact with the under bump metallizations (UBM) and/or board level metallizations on either side of the solder bump to form intermetallic compounds (IMCs) during solder reflow. In the modelling of the kinetics of the dissolution process of UBM into the liquid solder, the commonly used NernstBrunner (N-B) equation is found to have poor validity for these calculations for micro joints at 100 μm in diameter or less. Three bumping techniques, i.e. solder dipping (SD), solder paste stencil printing followed by reflow (SPR) and electroplating of solders and subsequent reflow (EPR), are used to investigate the interfacial interactions of molten Sn/Sn-rich solders, i.e. pure Sn, Sn-3.5Ag, and Sn-3.8AgO.7Cu, on electroless nickel immersion gold (ENIG) and copper pads at 240°C. The resultant bulk and interfacial microstructures from a variety of pad sizes, ranging from 1 mm down to 25 μm, suggest that in general the small bumps contain smaller β-Sn dendrites and Ag₃Sn IMC particles, nevertheless the interfacial IMC is thicker in the smalI bumps than in the large bumps. In addition, one and two-dimensional combined thermodynamic and kinetic models have been developed to assist the understanding of the kinetics of interdiffusion and the formation of interfacial intermetallic compounds during reflow. Both the experimental results and theoretical predictions suggest that the solder bump size and geometry can influence the as-soldered microstructure, and therefore this factor should be taken into consideration for the design of future reliable ultrafine Ph-free solder joints.

This work is considered about changes of electric conductivity in lead-free soldered joint's affected by current and thermal stress. The theoretical part describes factors influencing the solder joint electric conductivity and solder joint reliability. The basis of the practical part is the design of the testing method of the soldered joint's electric conductivity. The aim of this part is to measure and observe changes of solder joint electric conductivity after current and thermal stress in various material a procedural combinations.

This research work is dealing with impact and size of the thermoelectric that may influence DC circuits. Main part of this thesis is to build experimental equipment for measurement of the thermoelectric and following usage this equipment for detection of the size the thermoelectric voltage for lead and lead-free solders. The theoretical part of this work deals with creation and usage of the thermoelectric in electrical engineering industry. In this particular part of this work is an example how the thermoelectric influence DC circuits. Then I describe thermoelectric generation from the motherboard to the die. The practical part of this thesis is focused on the development of the equipment for measuring of the thermoelectric of different types of materials. The Thermoelectric has been measured on two types of the lead, six types lead-free solders and on four types of the thermocouple wires. It has been measured within the range from 0°C to 80°C. In the end of this work is summary, where is reviewed witch of solders is the best for an applications affected by the thermoelectric.

The project contains theoretical research of electrotechnical manufacture for lead-free reflow soldering. It contains characterization of soldering processes. Includes variations of solder paste printing, principles of part placing and also reflow soldering process. The project appoints possibilities of testing solder joints strength, mainly focused on mechanical vibrations. It describes a design and preparation of solder joint strength test methods by mechanical vibrations. It compares influence of vibrations on part types and solder alloys.

The thesis deals issue of the solder joint reliability and diagnostics. The manufacturing technology of electronics currently features a very high level of perfection. A large number of electrical devices ends its functional life due to solder joint failure. The objective of presented research consists studies of processes taking place in the solder joint due to soldering and after soldering. To this end, I will employ several methods of diagnostics. Noise based methods of solder joint measurement was evaluated. Based on a detailed study and understanding of processes it can be solder joint reliability predicted.

Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module. / Ph. D.

The appropriate selection of failure criterion for solder joint studies is necessary to correctly estimate reliability life. The objective of this study is to compare the effect of different failure criteria on the reliability life estimation. The four failure criteria in this study are a 20% resistance increase defined in the IPC-9701A standard, a resistance beyond 500 Ω, an infinite resistance (hard open), and a failure criterion based on X-bar and R control charts. Accelerated thermal cycling conditions of a low-silver BGA study included 0°C to 100 °C with ten minute dwell times and -40°C to 125°C with ten minute dwell times. The results show that the life estimation based on X-bar and R failure criterion is very similar to the life estimation when a 20% resistance increase defined in the IPC-9701A failure criterion is used. The results also show that the reliability life would be overestimated if the failure criterion of a resistance threshold of 500 Ω or an infinite resistance (hard open) is used.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.

abstract: Thousands of high-resolution images are generated each day. Segmenting, classifying, and analyzing the contents of these images are the key steps in image understanding. This thesis focuses on image segmentation and classification and its applications in synthetic, texture, natural, biomedical, and industrial images. A robust level-set-based multi-region and texture image segmentation approach is proposed in this thesis to tackle most of the challenges in the existing multi-region segmentation methods, including computational complexity and sensitivity to initialization. Medical image analysis helps in understanding biological processes and disease pathologies. In this thesis, two cell evolution analysis schemes are proposed for cell cluster extraction in order to analyze cell migration, cell proliferation, and cell dispersion in different cancer cell images. The proposed schemes accurately segment both the cell cluster area and the individual cells inside and outside the cell cluster area. The method is currently used by different cell biology labs to study the behavior of cancer cells, which helps in drug discovery. Defects can cause failure to motherboards, processors, and semiconductor units. An automatic defect detection and classification methodology is very desirable in many industrial applications. This helps in producing consistent results, facilitating the processing, speeding up the processing time, and reducing the cost. In this thesis, three defect detection and classification schemes are proposed to automatically detect and classify different defects related to semiconductor unit images. The first proposed defect detection scheme is used to detect and classify the solder balls in the processor sockets as either defective (Non-Wet) or non-defective. The method produces a 96% classification rate and saves 89% of the time used by the operator. The second proposed defect detection scheme is used for detecting and measuring voids inside solder balls of different boards and products. The third proposed defect detection scheme is used to detect different defects in the die area of semiconductor unit images such as cracks, scratches, foreign materials, fingerprints, and stains. The three proposed defect detection schemes give high accuracy and are inexpensive to implement compared to the existing high cost state-of-the-art machines. / Dissertation/Thesis / Ph.D. Electrical Engineering 2010

To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package.