Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module. / Ph. D.

With the potential to improve upon silicon (Si ) based power electronics exhausted, the push for improvement now lies with wide bandgap (WBG) materials like gallium nitride (GaN). With a larger bandgap, higher electron mobility, and higher electrical field strength than Si, GaN high electron mobility transistors (HEMTs) can have lower on-state losses and higher switching frequencies in a smaller package. This makes GaN HEMTs an attractive choice for compact, high efficiency power devices. However, the package designs used for Si cannot be used for GaN HEMTs, requiring novel, chip-scale designs that are optimized for low electrical parasitics and low thermal resistance. Recent Center for Power Electronics (CPES) research culminated in a printed circuit board-direct bonded copper (PCB-DBC) hybrid package to house a 650 V, 150 A GaN HEMT. Called the PCB-Interposer-on-DBC package, it utilizes a DBC for heat extraction while using vertical pin interconnects to minimize electrical parasitics. Previous work did not investigate the design's locations of expected failure or reliability. With thermally generated mechanical fatigue a consistent cause of electronics failure, it must be investigated for the design to move beyond the prototyping phase. Thermo-mechanical fatigue failure is the brittle fracture of bonds caused by thermally induced warpage. The thermal warpage is the consequence of the bonded package components having a coefficient of expansion (CTE) mismatch while being subjected to temperature changes during operation. Multiphysics simulation software have previously quantified the fatigue placed on bonds exposed to these cyclic conditions, with a common metric being the volume-averaged inelastic strain energy density gained per cycle (ΔWavg). ΔWavg can identify which bonds are subjected to the greatest amount of fatigue and will thus fail first, and then quantify the effect of design alterations on those vulnerable bonds. A common design alteration seen in solder ball packaging is adding a polymeric material that encapsulates the bonds. If the polymer has a CTE like that of the package substrates and an elastic modulus (E) exceeding 1 GPa, it constrains the thermal warpage and lowers bond fatigue. This thesis uses thermo-mechanical simulations to provide evidence on which bonds fail first in the package, and that material-based methods of fatigue reduction used in solder ball packing apply to this novel package. Chapter 1 explains how a desire to reduce the cost and increase the performance of electric vehicles led to the development of the PCB-Interposer-on-DBC design, and that the package's response to thermo-mechanical fatigue is unknown. The concepts of thermo-mechanical fatigue and using encapsulants to reduce it are established, along with how simulations are used to study said fatigue. Chapter 2 serves two purposes, the first being an explanation of the simulation settings and metrics used to establish the quality and assumptions used, and the second being a beginners guide on how to create these simulations. Chapter 3 identifies the most probable locations of initial package failure and identifies what encapsulants minimize ΔWavg on those locations. The sintered silver bond expected to fail first is the Internal Gate bond, and an encapsulant with the maximum possible E and 8 ppm/°C minimizes ΔWavg. The Sn60Pb40 bond expected to fail first is the External Source 4 bond and using an encapsulant with the maximum possible E and a CTE of 24 ppm/°C minimizes ΔWavg. While ΔWavg cannot determine which of the two bonds fails first as they are made of different materials, the Internal Gate is prioritized as it has a higher per-cycle fatigue and to prevent loss of the gate signal. Chapter 4 demonstrates how to perform a brief encapsulant study while ranking the expected cycles to failure when using four different encapsulant options. The first two options are to use no encapsulant or silicone gel. As the elastic modulus of silicone gels are too low to restrict or couple the thermally generated warpage, using silicone gel results in a ΔWavg comparable to using no encapsulant. The rigid encapsulant with the properties most like the optimal encapsulant identified for Internal Gate has the lowest ΔWavg¬ of the encapsulants tested. Guidelines are established for what properties an encapsulant must have to outperform said rigid encapsulant. This work uses simulations to provide evidence that encapsulant methods used in ball grid array (BGA) packaging to reduce fatigue apply to a novel GaN HEMT package. By identifying the first-failure locations of the package, establishing what existing encapsulant should be used, and what encapsulation it should eventually be replaced with, these results provide the groundwork for both experimental temperatures cycling and more complex simulations. Such work fills the gap in understanding the reliable lifetime and common failure mechanisms of the PCB-Interposer-on-DBC package. / Master of Science / In modern engineering, the cause of failure in a well-designed electronic device is typically not a single event. Rather, it is the culmination of many smaller events that each cause a minor amount of damage. This cycle of repeated, minor damage is called fatigue. When working with power or IC electronics, the most common type of fatigue occurs due to the device's changing temperature. Electronics undergo continuously changing temperatures due to the environment and their own energy losses, causing repeated cycles of heating and cooling. All materials expand upon heating and contract upon cooling , and the magnitude of this change is the coefficient of thermal expansion (CTE). Electronic devices are comprised of dissimilar materials, so disparate components will expand and contract at different rates. Holding these disparate materials together are bonds, which in the process of holding this warped structure together, also deform. This deformation causes permanent damage, which accumulates in the bonds until they break. As these bonds often serve as pathways for the electrical signal or heat extraction, their failure either degrades or breaks the electrical devices. While preventing bond fatigue is impractical, there are strategies to extend the operating lifetime. A common option used elsewhere is to encase the bonds with a polymer. If the polymer's properties are carefully selected, they can reduce the structural warpage, thereby reducing the fatigue on the bonds. Previous Center for Power Electronics (CPES) research has culminated in a new electronics device called the Printed Circuit Board-Interposer-on-Direct Bonded Copper package (PCB-Interposer-on-DBC package). While general trends suggest which bonds will fail first and what kind of polymers reduce fatigue, this information has not yet been confirmed. This thesis uses computer simulations to identify which bonds will likely fail first, and to provide evidence that existing methods for reducing fatigue are viable for this unique package. The simulations work by subjecting a 3D model to a cycle of heating and cooling, called a temperature cycle, and quantifying the damage sustained by the bonds for every cycle. Chapter 1 describes the relevant details leading to this package design, the importance of thermo-mechanical reliability in the design of electronics, and how to use simulation software to quantify reductions in bond fatigue. Chapter 2 explains how to set up these simulations and evaluate their quality. Chapter 3 identifies the initial locations of package failure and identifies what are the most optimal encapsulants to use. Chapter 4 identifies what existing encapsulant will maximize the package lifetime in experimental temperature cycling.

This research is focused on the processing of an innovative three-dimensional packaging architecture for power electronics building blocks with soldered device interconnections and subsequent characterization of the module's critical interfaces. A low-cost approach termed metal posts interconnected parallel plate structure (MPIPPS) was developed for packaging high-performance modules of power electronics building blocks (PEBB). The new concept implemented direct bonding of copper posts, not wire bonding of fine aluminum wires, to interconnect power devices as well as joining the different circuit planes together. We have demonstrated the feasibility of this packaging approach by constructing PEBB modules (consisting of Insulated Gate Bipolar Transistors (IGBTs), diodes, and a few gate driver elements and passive components). In the 1st phase of module fabrication with IGBTs with Si₃N₄ passivation, we had successfully fabricated packaged devices and modules using the MPIPPS technique. These modules were tested electrically and thermally, and they operated at pulse-switch and high power stages up to 6kW. However, in the 2nd phase of module fabrication with polyimide passivated devices, we experienced significant yield problems due to metallization difficulties of these devices. The under-bump metallurgy scheme for the development of a solderable interface involved sputtering of Ti-Ni-Cu and Cr-Cu, and an electroless deposition of Zn-Ni-Au metallization. The metallization process produced excellent yield in the case of Si₃N₄ passivated devices. However, under the same metallization schemes, devices with a polyimide passivation exhibited inconsistent electrical contact resistance. We found that organic contaminants such as hydrocarbons remain in the form of thin monolayers on the surface, even in the case of as-received devices from the manufacturer. Moreover, in the case of polyimide passivated devices, plasma cleaning introduced a few carbon constituents on the surface, which was not observed in the case of Si₃N₄ passivated devices. X-Ray Photoelectron Spectroscopy (XPS) Spectra showed evidence of possible carbon contaminants, such as carbide (~282.9eV) and graphite (~284.3eV) on the surface at binding energies below the binding energy of the hydrocarbon peak (C 1s at 285eV). Whereas above the hydrocarbon peak energy level, carbon-nitrogen compounds, single bond carbon compounds (~285.9eV) and double bond carbon compounds (~288.5eV) were evident. The majority of the carbon composition on the pad surface was associated with hydrocarbons, which were hydrophobic in nature, thus making the device contact pad less wettable. XPS data showed that, after the plasma cleaning process, absorbed monolayers on the Si₃N₄ passivated and polyimide passivated surfaces consisted of different chemical compositions and accordingly, the attraction forces of these absorbed layers are also different, which affects the bonding properties of the subsequent metallization, resulting in different contact resistances. On the other hand, with an electroless Zn-Ni-Au deposition, it was found that the polyimide passivation on the devices degraded due to due alkaline exposure in the plating baths, thus lowering the device breakdown voltage significantly. Furthermore, interfacial thermal resistances of solder preform, solder paste and silver epoxy (between the power module and the heat spreader) were characterized for process optimization. Void content at the resulting interface was found to be dependent on the flux content and flux activity. Solder preform with no-clean flux, reflowed in nitrogen results in the least resistant and minimized void-content interface. It is most likely that the flux added to the preform had a higher fluxing action than the flux contained in the solder paste. On the other hand, the outgassing of the entrapped flux profoundly affects the void formation and a lower void content indicates a lesser amount of trapped flux. In the case of a solder paste, the flux is in direct contact with the surface oxide of the powders and the surface to be soldered. Consequently, during reflow, any residual oxide can be expected to have some flux adhered to it. In the case of solder preform with added flux, the higher activity flux eliminated the oxide more rapidly and more thoroughly, thus leaving fewer spots for the flux to adhere to. Void contents in all cases of nitrogen reflow are consistently lower than the air-reflowed samples. Silver epoxy with a higher thermal conductivity (60W/mK) than Pb-Sn eutectic solder did not produce low-resistance interfaces. We found that thermal conductivity of the interface material is not the most crucial factor in reducing thermal resistance, rather it is the contact thermal resistance of the interfaces, which constitutes the largest part of the total interfacial thermal resistance. Process optimization with applied pressure and nitrogen reflow resulted in a significant lowering of contact resistance (from 0.55°C/W to 0.25°C/W) for the solder preform interfaces. We concluded that contact resistance needs to be duly accounted for in thermal modeling for an accurate representation of an interface; at the same time, the module attachment process must be tailored to reduce contact resistance for improved thermal management. / Ph. D.

This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power electronics packaging. In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time. To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials. From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and plastic strain in the solder layer were reduced by 18.7% and 67.8%, respectively. However, the thermal impedance of the power module increases with reduction of the stress. Therefore, the trade-off between these two factors was discussed. To verify better reliability brought by the trenched copper plate structure, twenty-four samples with three different copper plate structures were fabricated and thermally cycled from -40°C to 105°C. To detect the failure at the bonding layer, the curvature of these samples were measured using laser scanning before and after cycling. By monitoring the change of curvature, the degradation of bonding layer can be detected. Experimental results showed that the samples with different copper plate structure had similar curvature before thermal cycle. The curvatures of the samples with single copper plate decreased more than 80% after only 100 cycles. For the samples with 2 × 2 copper plate and the samples with 3 × 3 copper plate, the curvatures became 75.8% and 77.5% of the original values, respectively, indicating better reliability than the samples with single copper plate. The x-ray pictures of cross-sectioned samples confirmed that after 300 cycles, the bonding layer for the sample with single copper plate has many cracks and delaminations starting from the edge. / Ph. D.

L'utilisation du diamant comme composant d'électronique de puissance est une perspective intéressante tant en ce qui concerne les applications hautes température que forte puissance. La problématique principale de ces travaux réalisés dans le cadre du programme Diamonix, réside dans l'étude et l'élaboration d'un packaging permettant la mise en oeuvre d'une puce diamant devant fonctionner à des températures variant entre -50°C et 300°C. Nous nous sommes intéressés au choix des matériaux de connexion de la puce avec son environnement. Suite à l'étude bibliographique, nous proposons différentes solutions de matériaux envisageables pour le substrat métallisé, les brasures et les métallisations. Dans un second temps, les différents éléments ont été réalisés puis caractérisés à partir d'essais de nanoindentation et de nanorayage. Des essais mécaniques ont permis de caractériser le comportement élastoviscoplastique et l'endommagement des brasures. Ces derniers essais ont servi de base expérimentale à l'identification des paramètres d'un modèle de comportement viscoplastique couplé avec l'endommagement et qui a été spécialement élaboré pour cette étude. Le modèle de comportement a été implémenté dans un code de calcul par éléments finis via une sous-routine. Il permet notamment de simuler le processus de dégradation d'un assemblage. Enfin, ce modèle de comportement a été mis en oeuvre dans des modélisations thermomécaniques de différentes configurations de véhicules test. / Use of diamond as constitutive component in power electronics devices is an interesting prospect for the high temperature and high power applications. The main challenge of this research work included in the Diamonix program is the study and the elaboration of a single-crystal diamond substrate with electronic quality and its associated packaging. The designed packaging has to resist to temperatures varying between -50°C and 300°C. We contributed to the choice of the connection materials intended to be used in the final test vehicle and which can handle such temperature gaps. In the first part, we present a state-of-the-art of the various materials solutions for extreme temperatures. Following this study, we propose a set of materials which considered as potential candidates for high temperature packaging. Special focus is given for the most critical elements in power electronic assemblies which are metallizations and solders. Once the materials choice carried out, thin substrate metallizations, solders and DBC coatings are studied using nanoindentation and nanoscratch tests. Mechanical tests were also carried out on solders to study their elastoviscoplastic and damage behavior. The experimental results are used as database for the identification of the parameters of the viscoplastic model coupled with a porous damage law, worked out for the case of solders. The behavior model is implemented as a user subroutine UMAT in a FE code to predict the degradation of a 2D power electronic assembly and various materials configuration for a 3D test vehicle.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are favored for their smaller specific on-resistance, lower switching losses, and higher theoretical temperature limits as compared to traditional silicon (Si) power switches. They have the potential to dramatically increase the power density and efficiency of power electronics systems by replacing traditional Si-based switches. However, GaN HEMTs have a faster switching speed compared to their Si-based counterparts. Minimizing the parasitic loop inductances of the GaN HEMT package is crucial for reducing electromagnetic interference (EMI) noise and voltage spikes. Another concern with GaN HEMTs comes from their lower thermal conductivity and smaller die size. The HEMTs generally have a higher heat flux density, and accordingly, demand better heat dissipation. Thus, innovations are needed for making GaN HEMT packages with low parasitic inductances and higher thermal performances to further their applications in high-frequency, high-power-density converters. To reduce loop inductance, other researchers have embedded GaN HEMTs in a printed circuit board (PCB) and used plated vias for interconnections and heat dissipation. However, this approach requires more complex manufacturing steps and has lower thermal performance. This dissertation introduces different embedded packaging techniques for 650V, 150A GaN HEMTs; this method involves interconnecting the bare chips between direct-bonded copper (DBC) and a PCB or between two DBCs, as discussed in Chapter 2. Vertical interconnections by gold pins and silver rods are introduced and implemented in embedded packages to limit the parasitic loop inductance within 1.5 nH and parasitic resistances within 1.5 mΩ. The thermal performance of the embedded GaN HEMT packages is experimentally verified in Chapter 2; then, the junction-to-case thermal resistance (RthJC) measurement is discussed in Chapter 3. The common temperature-sensitive electrical parameters (TSEPs) of a GaN HEMT for junction temperature measurement lack sufficient sensitivity or stability due to the electron-trapping effect. The non-uniform distribution of the case temperature and a large temperature gradient between the case and heatsink also make it difficult to accurately measure the case temperature. In Chapter 3, gate-to-gate resistance (Rg2g) is selected as the TSEP for junction temperature measurement. The stacked thermal interface material (TIM) technique was used to reduce errors in case temperature measurement. This technique was implemented in a custom GaN HEMT package and in embedded GaN HEMT packages for measuring junction-to-case thermal resistance. The discrepancy between measurement and simulation is less than 20%, and the junction-to-case thermal resistance for embedded packages is within 0.1 °C/W. Chapter 4 evaluates the reliability of the GaN HEMT embedded packages developed in Chapter 2 by utilizing a power cycling test. Monitoring the junction temperature of the embedded packages online is challenging during the power cycling test. Other approaches have used the on-resistance as the TSEP in order to monitor junction temperature for GaN HEMTs but this is not accurate due to electron trapping. As discussed in Chapter 3, Rg2g is chosen as the TSEP to monitor the junction temperature without worrying about the influence of electron trapping, and this approach cycles the embedded packages at 75 A from 25°C to 125°C. The packages can endure 23,000 power cycles before failure. This work is the first to develop, fabricate, and characterize embedded packages for 650V, 150A GaN HEMT bare chips. These embedded packages with high-power-rated GaN HEMT bare dice provide an opportunity to reduce the number of paralleled power switches, reduce the system's cooling size, and increase the system's power density. In addition, this work is the first to develop the junction-to-case thermal resistance measurement technique by gate-to-gate electrical resistance and stacked-TIM for GaN HEMT packages. The technique helps enable solid thermal design for power electronics systems. / Doctor of Philosophy / Power switches are everywhere in our daily life. They are the fundamental elements in power converters for converting power to electric vehicles. As global power demand for these applications continues to increase, high levels of both efficiency and power density are crucial for power switches. However, traditional silicon-based switches are already very mature, and their properties are very close to their theoretical limits. For further improvement, researchers have tried to replace traditional Si switches with wide-bandgap switches, which have much higher theoretical limits. Gallium nitride high-electron-mobility transistors (GaN HEMTs) are one of the candidates. However, packaging these switches (GaN HEMTs) is challenging due to their initial properties. They naturally switch very quickly and have smaller sizes compared to traditional Si-based switches. The fast switching speed brings high dv/dt and di/dt during the switching period. It causes voltage spikes and electromagnetic interference (EMI) issues. And the smaller size contributes to higher heat flux density, thus requiring more efficient heat dissipation. To solve the challenge of packaging GaN HEMTs, this dissertation has developed embedded packaging techniques to achieve quiet switching and good heat dissipation. These packaging techniques enable GaN HEMTs' advantages and increase the power density and efficiency of power electronics systems. To experimentally verify the thermal performance of the embedded packages developed a junction-to-case thermal resistance measurement technique was introduced. The thermal resistance of a custom GaN HEMT package was measured, as were those of the embedded packages CPES also developed. The simulation results and the experimental results are close to each other. Finally, to further evaluate whether or not the newly developed embedded packages are reliable, power cycling tests were carried out at I = 75 A. The packages survived over 23,000 cycles before failure.

L’accroissement des besoins en énergie électrique pour les systèmes embarqués et leur augmentation de puissance nécessitent de concevoir des systèmes d’électronique de puissance toujours plus performants. Une solution d’avenir concerne la mise en œuvre de composants à base de diamant qui permettent l’augmentation conséquente des tensions et courants mis en jeux, mais aussi de la température maximale de jonction admissible. Le cadre de ces travaux est celui du projet de recherche Diamonix 2, qui concerne l’étude et l’élaboration d’un composant diamant fonctionnant à haute température. L’objectif du travail doctoral présenté ici est l’étude du packaging haute température de ce type de composant diamant. Plusieurs choix de matériaux et de techniques aptes à l’élaboration d’un assemblage de puce diamant sur un substrat métallisé ont été effectués. La caractérisation microstructurale et mécanique de trois types de jonctions ont été réalisées (refusion d’un alliage AuGe, frittage de nano pâtes d’argent et diffusion en phase solide d’indium dans des couches d’argent). Des essais mécaniques de cisaillement de divers assemblages ont permis d’évaluer le comportement thermomécanique des jonctions et des interfaces. Les essais de cisaillement ont servi à l’identification inverse des paramètres interfaciaux d’un modèle de zones cohésives, pour différents types d’interfaces. Des modèles éléments finis d’assemblage, incluant le comportement viscoplastique des jonctions et des lois d’endommagent des interfaces, ont servi à simuler le comportement thermomécanique du packaging d’un composant diamant. / The increase of electric power demand for embedded systems requires more efficient power electronics modules. A solution to reach this goal relates to the use of diamond-based components that allow high voltage, current density and the maximum allowable junction temperature. The framework is the same as that of the Diamonix 2 research project, which involves the elaboration and the study of a diamond-based die dedicated to high temperature environment. The purpose of the present work is to optimize and simulate the thermomechanical behavior of high temperature diamond die packaging. To reach this goal, the choice of materials that allow high temperature assemblies of diamond die/ceramic substrate was done (AuGe solder alloy, sintering of nano-silver paste, transient liquid phase bounding of indium in silver layers). Microstructural and mechanical characterization of the attachment and the diamond die/junction was realized. Nanoindentation and shear tests are performed for the mechanical characterization. Shear tests results carried out on the two assemblies have been used to identify the interfacial parameters of the bilinear cohesive zone model (CZM) for the diamond die/junction and ceramic substrate/junction interfaces. Finite element modelling of the diamond component packaging including viscoplastic behavior of the junctions and damage law of the interfaces of assemblies were built.

Le développement de composants de puissance à base de carbure de silicium (SiC) permet la réalisation d’interrupteurs pouvant fonctionner au-delà de 200°C. Le silicium présente plus de limitations au niveau physique du matériau qu’au niveau des technologies d’assemblages. Le SiC est un matériau semi-conducteur grand gap ce qui permet d’obtenir des courants de fuite inverse qui restent faibles à haute température ; d’où un fort intérêt pour des applications haute température. Mise à part son utilisation à des températures pouvant dépasser les 300°C, c’est un matériau qui permet aussi d’augmenter les fréquences de commutation ainsi que la densité de puissance par rapport à des composants à technologie silicium. Ceci en fait un candidat idéal pour des applications forte puissance dans le domaine de la traction, des protections de réseaux électriques ou de la transmission et de la distribution d’énergie. L’utilisation du SiC pour une application haute température pose le problème de son packaging, des choix de matériaux et de sa configuration. Cette thèse a pour but d’effectuer une étude de fiabilité et de durée de vie des briques technologiques d’assemblage et de connexions nécessaires à la réalisation d’un cœur de puissance haute température à base de JFET SiC. Une étude des différentes technologies d’assemblages de convertisseurs de puissance haute température est effectuée afin de définir différentes briques technologiques constitutives de ces systèmes. Cette première étude nous permet de procéder à une sélection de certaines technologies d’assemblages comme le frittage de pâtes d’argent pour la technologie de report de puces. Ces briques technologiques feront l’objet d’études plus approfondies allant de la réalisation de véhicules tests jusqu’à la mise au point des essais de cyclages associés aux techniques d’analyse nécessaires à l’étude de leur défaillance.Les études expérimentales concernent des essais de cyclage passif et de stockage thermique, l’apparition de délaminages en cours de cyclage thermique (scan acoustique, RX), le report par frittage de pâtes d’argent nano et microscopiques et la caractérisation électrique et thermique (Rth, I[V]). / The development of power components based on silicon carbide (SiC) allows for the design of power converter operating at high temperature (above 200 or 300°C). SiC is a semiconductor material with a large band gap that not only can operate in temperatures exceeding 300°C but also offers fast switching speed, high voltage blocking capability and higher thermal conductivity compared to silicon technology components. The classical die attach technology uses high temperature solder alloys which melt at around 300°C. However, even a soldered die attach with such high melting point can only operate up to a much lower temperature. Alternative die attach solutions have recently been proposed: Transient Liquid Phase Bonding, soldering with higher melting point alloys such as ZnSn, or silver sintering.Silver sintering is a very interesting technology, as silver offers very good thermal conductivity (429W/m.K, better than copper), relatively inexpensive (compared to alternative solutions which often use gold), and has a very high melting point (961°C).The implementation of two silver-sintering processes is made: one based on micrometer-scale silver particles, and one on nano-meter-scale particles. Two substrate technologies are investigated: Al2O3 DBC and Si3N4 AMB. After the process optimization, tests vehicles are assembled using nano and micro silver particles paste and a more classical high-temperature die attach technology: AuGe soldering. Multiple analyses are performed, such as thermal resistance measurement, shear tests and micro-sections to follow the evolution of the joint during thermal cycling and high-temperature storage ageing.