This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power electronics packaging. In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time. To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials. From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and plastic strain in the solder layer were reduced by 18.7% and 67.8%, respectively. However, the thermal impedance of the power module increases with reduction of the stress. Therefore, the trade-off between these two factors was discussed. To verify better reliability brought by the trenched copper plate structure, twenty-four samples with three different copper plate structures were fabricated and thermally cycled from -40°C to 105°C. To detect the failure at the bonding layer, the curvature of these samples were measured using laser scanning before and after cycling. By monitoring the change of curvature, the degradation of bonding layer can be detected. Experimental results showed that the samples with different copper plate structure had similar curvature before thermal cycle. The curvatures of the samples with single copper plate decreased more than 80% after only 100 cycles. For the samples with 2 × 2 copper plate and the samples with 3 × 3 copper plate, the curvatures became 75.8% and 77.5% of the original values, respectively, indicating better reliability than the samples with single copper plate. The x-ray pictures of cross-sectioned samples confirmed that after 300 cycles, the bonding layer for the sample with single copper plate has many cracks and delaminations starting from the edge. / Ph. D.

Double-sided module exhibits electrical and thermal characteristics that are superior to wire-bonded counterpart. Such structure, however, induces more than twice the thermo-mechanical stress in a single-layer structure. Compressive posts have been developed and integrated into the double-sided module to reduce the stress to a level acceptable by silicon dice. For a 14 mm x 21 mm module carrying 6.6 mm x 6.6 mm die, finite-element simulation suggested an optimal design having four posts located 1 mm from the die; the z-direction stress at the chip was reduced from 17 MPa to 0.6 MPa. / Ph. D.

La gestion, la manipulation et le stockage de données sont aujourd’hui de réels challenges. Pour supporter cette réalité, le besoin de technologies mémoires plus efficaces, moins énergivores, moins coûteuses à fabriquer et plus denses que les technologies actuelles s’intensifie. Parmi les technologies mémoires émergentes se trouve la technologie mémoire résistive, dans laquelle l’information est stockée sous forme de résistance électrique au sein d’une couche d’oxyde entre deux électrodes conductrices. Le plus gros frein à l’émergence de tels dispositifs mémoires résistives en matrices passives à deux terminaux est l’existence d’importants courants de fuites (ou sneak paths) venant perturber l’adressage individuel de chaque point de la matrice. Les dispositifs complementary resistive switching (CRS), consistant en deux dispositifs OxRRAM agencés dos à dos, constituent une solution performante à ces courants de fuites et sont facilement intégrables dans le back-end-of-line (BEOL) de la technologie CMOS. Cette thèse a permis d’apporter la preuve de concept de la fabrication et de l’intégration de dispositifs CRS de façon 3D monolithique dans le BEOL du CMOS. / In our digital era, management, manipulation and data storage are real challenges. To support this reality the need for more efficient, less energy and money consuming memory technologies is drastically increasing. Among those emerging memory technologies we find the oxide resistive memory technology (OxRRAM), where the information is stored as the electrical resistance of a switching oxide in sandwich between two metallic electrodes. Resistive memories are really interested if used inside passive memory matrix. However the main drawback of this architecture remains related to sneak path currents occurring when addressing any point in the passive matrix. To face this problem complementary resistive switching devices (CRS), consisting in two OxRRAM back to back, have been proposed as efficient and costless BEOL CMOS compatible solution. This thesis brought the proof of concept of fabrication and 3D monolithic integration of CRS devices in CMOS BEOL.