To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.

To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes / The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls

Shadows have captivated humanity since the dawn of time; with the current age being no exception – shadows are core to realism and ambience, be it to invoke a classic Baroque interplay of lights, darks and colours as the case in Rembrandt van Rijn’s Militia Company of Captain Frans Banning Cocq or to create a sense of mystery as found in film noir and expressionist cinematography. Shadows, in this traditional sense, are regions of blocked light – the combined effect of placing an object between a light source and surface. This dissertation focuses on real-time shadow generation as a subset of 3D computer graphics. Its main focus is the critical analysis of numerous real-time shadow rendering algorithms and the construction of an empirically derived system for the high-speed rendering of shadows. This critical analysis allows us to assess the relationship between shadow rendering quality and performance. It also allows for the isolation of key algorithmic weaknesses and possible bottleneck areas. Focusing on these bottleneck areas, we investigate several possibilities of improving the performance and quality of shadow rendering; both on a hardware and software level. Primary performance benefits are seen through effective culling, clipping, the use of hardware extensions and by managing the polygonal complexity and silhouette detection of shadow casting meshes. Additional performance gains are achieved by combining the depth-fail stencil shadow volume algorithm with dynamic spatial subdivision. Using this performance data gathered during the analysis of various shadow rendering algorithms, we are able to define a fuzzy logic-based expert system to control the real-time selection of shadow rendering algorithms based on environmental conditions. This system ensures the following: nearby shadows are always of high-quality, distant shadows are, under certain conditions, rendered at a lower quality and the frames per second rendering performance is always maximised. / Dissertation (MSc)--University of Pretoria, 2009. / Computer Science / unrestricted

V této práci představujeme blokovou metodu pro zlepšení lokality v cache paměti u výpočtů typu stencil a dva nástroje, Pluto a PATUS, které tuto metodu používají ke generování optimalizovaného kódu. Provádíme různá měření a zkoumáme zrychlení výpočtu při použití různých optimalizací. Nakonec implementujeme vyhlazovací krok v multigridu s různými optimalizacemi a zkoumáme jak se tyto optimalizace projeví na výkonu multigridu.

This thesis focuses on the topic of stencil painting in Central Europe. Based on the review of literature the current state of research is described and the technology is placed in the broader context of the decorative techniques used in the Middle Ages. Attention is paid to the history, process of making of the templates, method of their printing, the typology of used designs, the question of performing artists or craftsmen and wide possibilities of its application for the panel or mural paintings. The main focus of the thesis is the use of stencil painting and its specifics in the case of use for the polychrome of flat wooden ceilings and mobiliary in the churches interiors. The motifs used for their decoration are examined with regard to iconography, considered is also the possibility of the existence of overall iconographic program. The second part of the thesis consists of a catalogue with locations, where the stencil paintings have been used for decoration of flat ceilings or mobiliary in Czech, Slovak and Polish Republic. Keywords medieval art, stencil painting, ornament, Central Europe, wooden flat ceilings, mobiliary, polychrome, iconography

Dans cette thèse, nous montrons que les optimisations source-à-source sont un moyen efficace pour générer des programmes irréguliers ou parallèles performants à partir d'une implémentation. Après avoir présenté l'évolution des architectures des processeurs, nous proposons deux méthodes distinctes. La première pour extraire des codelets d'un programme irréguliers, les optimiser et prédire les performances du programme modifié. L'autre pour limiter l'impact des problèmes d'alignements dus à la vectorisation ou aux conflits de bancs. Nous présentons aussi différentes techniques de parallélisation, l'une générant des codelets parallèles, l'autre ordonnançant un graphe de taches sur un système hétérogène.

Conditioning geologic models to production data and assessment of uncertainty is generally done in a Bayesian framework. The current Bayesian approach suffers from three major limitations that make it impractical for field-scale applications. These are: first, the CPU time scaling behavior of the Bayesian inverse problem using the modified Gauss-Newton algorithm with full covariance as regularization behaves quadratically with increasing model size; second, the sensitivity calculation using finite difference as the forward model depends upon the number of model parameters or the number of data points; and third, the high CPU time and memory required for covariance matrix calculation. Different attempts were used to alleviate the third limitation by using analytically-derived stencil, but these are limited to the exponential models only. We propose a fast and robust adaptation of the Bayesian formulation for inverse modeling that overcomes many of the current limitations. First, we use a commercial finite difference simulator, ECLIPSE, as a forward model, which is general and can account for complex physical behavior that dominates most field applications. Second, the production data misfit is represented by a single generalized travel time misfit per well, thus effectively reducing the number of data points into one per well and ensuring the matching of the entire production history. Third, we use both the adjoint method and streamline-based sensitivity method for sensitivity calculations. The adjoint method depends on the number of wells integrated, and generally is of an order of magnitude less than the number of data points or the model parameters. The streamline method is more efficient and faster as it requires only one simulation run per iteration regardless of the number of model parameters or the data points. Fourth, for solving the inverse problem, we utilize an iterative sparse matrix solver, LSQR, along with an approximation of the square root of the inverse of the covariance calculated using a numerically-derived stencil, which is broadly applicable to a wide class of covariance models. Our proposed approach is computationally efficient and, more importantly, the CPU time scales linearly with respect to model size. This makes automatic history matching and uncertainty assessment using a Bayesian framework more feasible for large-scale applications. We demonstrate the power and utility of our approach using synthetic cases and a field example. The field example is from Goldsmith San Andres Unit in West Texas, where we matched 20 years of production history and generated multiple realizations using the Randomized Maximum Likelihood method for uncertainty assessment. Both the adjoint method and the streamline-based sensitivity method are used to illustrate the broad applicability of our approach.

The work deals with research and development of a new method for ball-attach process, resp. reballing process of solder bumps on package with solder ball terminals (BGA, CSP, SOP, etc.), based on research and optimization of the parameters of the final terminals. The output is specially modified templates designed for placement of solder balls before reflow soldering. Three materially different templates were investigated in the work, in addition to the commonly used stainless steel, two other newly designed templates, which used ceramic materials (96% Al2O3a AlN) with thick-layer resistance heating. Proven advantages of the method using templates directly heated by electric current are the reduction of the thermal load of BGA packages in the first soldering process, as well as the creation of a better connection between the metallization of the case and the solder ball after final soldering to the printed circuit board. During the research, development and optimization of the method, tests of the created solder bumps were performed from the point of view of mechanical strength and internal structure. In the next part of the work, a research of solder bumps soldered using infrared heaters was performed in order to determine the influence of the heat flow direction in the process of reflow soldering. The heaters were successively placed in three positions, i.e. heating from the bottom of the housing, heating from the top and both heaters simultaneously. After sample preparation, metallographic cuttings and etching, the analysis of the internal structure of the entire solder ball and the intermetallic layer at the interface of the solder and the solder pad was performed. The work represents not only a new method of soldering solder bumps, but also new knowledge to create their internal structure, which contributes to meeting the increasingly demanding requirements to achieve the required reliability and quality.

This master´s thesis deals with QFN packages soldering and technology procedures optimization. The aim of theoretical part is description of QFN packages, their assembly and reflow soldering on PCB in HONEYWELL. The aim of the practical part is to propose a method of measuring temperature and optimizing the thermal profiles of selected PCB with QFN packages by using convection (HONEYWELL) and infrared (BUT) reflow ovens. Comparison and evaluation of thermal profiles for 3 production PCBś with QFN packages using solder paste AIM NC257-2 were realised. The main part of master´s thesis are appearance evaluation of solder joints, preparing microsection and measuring intermetallic layers thickness by using the optical and the scanning electron microscopes, analysation and study of QFN defects created during soldering proces. These tests were performed with 2 production PCB´s. Optimization of SPI and soldering technology procedures where were analyzed QFN packages were processed on one type of PCB. Interesting part of this diplomma thesis is creating of the 3D heat transfer model of QFN package during the reflow soldering in SolidWorks.