Thesis (Ph. D.)--University of California, Riverside, 2008. / Includes abstract. Available via ProQuest Digital Dissertations. Title from first page of PDF file (viewed March 10, 2010). Includes bibliographical references (p. 126-135). Also issued in print.

Thesis (Ph. D.)--University of California, San Diego, 2001. / Vita. Includes bibliographical references.

The surface chemistry of GeH[subscript x] with dielectric surfaces is relevant to the application of germanium (Ge) nanocrystals for nanocrystal flash memory devices. GeH[subscript x] surface chemistry was first explored for thermally-grown SiO₂ revealing that GeH[subscript x] undergoes two temperature dependent reactions that remove Ge from the SiO₂ surface as GeH₄ and Ge, respectively. Ge only accumulates due to reactions between GeH[subscript x] species that form stable Ge clusters on the SiO₂ surface. Next, a Si-etched SiO₂ surface is probed by GeH[subscript x] revealing that the Si-etching defect activates the surface toward Ge deposition. The activation involves two separate reactions involving, first, the capture of GeH[subscript x] by the defect and second, a reaction between the captured Ge and remaining GeH[subscript x] species leading to the formation of Ge clusters. Reacting the defect with diborane, deactivates it toward GeH[subscript x] and also deactivates intrinsic hydroxyl groups toward GeH[subscript x] adsorption. A structure is proposed for the Si-etching defect. The surface chemistry of GeHx with HfO₂ is studied showing that the hafnium germinate that forms beneath the Ge nanocrystals exists as islands and not a continuous film. Annealing the hafnium germinate under a silane atmosphere will reduce it to Ge while leading to the deposition of hafnium silicate (HfSiO[subscript x]) and silicon (Si). Treating the HfO₂ with silane prior to Ge nanocrystal growth yields a surface with hafnium silicate islands on which Si also deposits. Ge deposition on this surface leads to the suppression of hafnium germinate formation. Electrical testing of capacitors made from Ge nanocrystals and HfO₂ shows that Ge nanocrystals encapsulated in Si/HfSiO[subscript x] layers have greatly improved retention characteristics. / text

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The purpose of this study is to explore the relationship between hit ratio of cache memory and design parameters. Cache memories are widely used in the design of computer system architectures to match relatively slow memories against fast CPUs. Caches hold the active segments of a program which are currently in use. Since instructions and data in cache memories can be referenced much faster than the time required to access main memory, cache memories permit the execution rate of the machine to be substantially increased. In order to function effectively, cache memories must be carefully designed and implemented. In this study, a trace-driven simulation study of direct mapped, associative mapped and set-associative mapped cache memories is made. In the simulation, cache fetch algorithm, placement policy, cache size and various parameters related to cache design and the resulting effect on system performance is investigated. The cache memories are simulated using the C language and the simulation results are analyzed for the design and implementation of cache memories. / Department of Physics and Astronomy

The performance of modern many-core systems depends on the effective use of their complex cache and memory structures, and this will likely become more pronounced with the impending arrival of on-chip 3D stacked and non-volatile off-chip byte-addressable memory. Yet to date, operating systems have not treated memory as a first class schedulable resource, embracing memory heterogeneity. This dissertation presents a new software abstraction, called ‘memory region’, which denotes the current set of physical memory pages actively used by workloads. Using this abstraction, memory resources can be scheduled for applications to fully exploit a platform's underlying cache and memory system, thereby gaining improved performance and predictability in execution, particularly for the consolidated workloads seen in virtualized and cloud computing infrastructures. The abstraction's implementation in the Xen hypervisor involves the run-time detection of memory regions, the scheduled mapping of these regions to caches to match performance goals, and maintaining region-to-cache mappings using per-cache page tables. This dissertation makes the following specific contributions. First, its region scheduling method proposes that the location of memory blocks rather than CPU utilization is the principal determinant where workloads are run. It proposes a new scheduling method, the region scheduling that the location of memory blocks determines where the workloads are run. Second, treating memory blocks as first-class resources, new methods for efficient cache management are shown to improve application performance as well as the performance of certain operating system functions. Third, explicit memory scheduling makes it possible to disaggregate operating systems, without the need to change OS sources and with only small markups of target guest OS functionality. With this method, OS functions can be mapped to specific desired platform components, such as file system confined to running on specific cores and using only certain memory resources designated for its use. This can improve performance for applications heavily dependent on certain OS functions, by dynamically providing those functions with the resources needed for their current use, and it can prevent performance-critical application functionality from being needlessly perturbed by OS functions used for other purposes or by other jobs. Fourth, extensions of region scheduling can also help applications deal with the heterogeneous memory resources present in future systems, including on-chip stacked DRAM and NUMA or even NVRAM memory modules. More generally, regions scheduling is shown to apply to memory structures with well-defined differences in memory access latencies.

Bibliography: leaves 156-165. / xvi, 174 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis analyses the design of a Dynamic RAM in gallium arsenide for use as a buffer in an ATM switch. The causes of leakage are investigated and methods to overcome or compensate the leakage are devised, resulting in a memory cell with a large storage time, high speed and low power dissipation. A 14 kbit RAM array is designed and laid out in gallium arsenide. The RAM array is designed to operate over a -25oC to +125oC temperature range using process parameters which vary by up to 2 [sigma] from typical. / Thesis (M.Eng.Sc.)--University of Adelaide, Dept. of Electrical & Electronic Engineering, 1996?

Thesis (M.S.)--University of Nevada, Reno, 2007. / "May, 2007." Includes bibliographical references (leaves 107-110). Online version available on the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.