This thesis investigates Electronic System Level (ESL) design flow by implementing some applications using CoWare ESL tool, ConvergenSC. There are three focuses in this thesis: basic cell modeling, system platform design, and system level architecture exploration. In the basic cell modeling, we adopt the system level language, SystemC, to describe the abstract behavior of various modules in Transaction Level Modeling (TLM). In system platform design, we use the ESL tool to create system platforms of different architectures, mainly AMBA-based system platforms. In the system architecture exploration, we analyze the simulation results in different system platform architectures and present several strategies (memory allocation, ASIC design, DMA, Pipeline Scheduling) to improve the overall system performance in the application example of MP3 decoder. The rough estimation of power and area is also included in the system architecture exploration stage.

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Commodity computer systems today do not provide system support for privacy. As a result, given the creation of new leak opportunities by ever-increasing software complexity, leaks of private data are inevitable. This thesis presents Suliban and Lacuna, two systems that allow programs to execute privately on commodity hardware. These systems demonstrate different points in a design space wherein stronger privacy guarantees can be traded for greater system usability. Suliban uses trusted computing technology to run computation-only code privately; we refer to this protection as "cloaking". In particular, Suliban can run malicious computations in a way that is resistant to analysis. Suliban uses the Trusted Platform Module and processor late launch to create an execution environment entirely disjoint from normal system software. Suliban uses a remote attestation protocol to demonstrate to a malware distribution platform that the environment has been correctly created before the environment is allowed to receive a malicious payload. Suliban's execution outside of standard system software allows it to resist attackers with privileged operating system access and those that can perform some forms of physical attack. However, Suliban cannot access system services, and requires extra case-by-case measures to get outside information like the date or host file contents. Nonetheless, we demonstrate that Suliban can run computations that would be useful in real malware. In building Suliban, we uncover which defenses are most effective against it and highlight current problems with the use of the Trusted Platform Module. Lacuna instead aims at achieving forensic deniability, which guarantees that an attacker that gains full control of a system after a computation has finished cannot learn answers to even binary questions (with a few exceptions) about the computation. This relaxation of Suliban's guarantees allows Lacuna to run full-featured programs concurrently with non-private programs on a system. Lacuna's key primitive is the ephemeral channel, which allows programs to use peripherals while maintaining forensic deniability. This thesis extends the original Lacuna work by investigating how Linux kernel statistics leak private session information and how to mitigate these leaks. / text

<p>Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life.</p><p>In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.</p>

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC). These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises. In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow. In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market. In this context, this thesis presents: - A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction. - The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices. - The implementation of a couple of two new tools of our own: - Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance. -Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis. To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature. Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool. We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization. Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benets are then discussed. We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore.

No description available.

Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life. In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.

System level parametric design of hybrid electric vehicles involves estimation of the power ratings as well as the values of certain parameters of the components, given the values of the performance parameters. The design is based on certain mathematical equations or ‘design rules’, which relate the component parameters and the performance parameters. The flow of the design algorithm is uni-directional and fixed, and cannot be altered. This thesis proposes a new method for such parametric design, called omni- directional design, which does not have a fixed sequence like the conventional design, but can start with any parameters of the designer’s choice. The designer is also able to specify the input parameters over a range, instead of a point (one, fixed value) input. Scenarios having a point input, but values of an output which can vary over a range for the point input, can also be studied.

Energy consumption will reduce the battery life time and increase the weight and cost of mobile devices. Low-power design methods become an important issue of SOC. Until now, there is no commercial power estimates software in system-level. Users must add power estimation to SystemC simulation environment by themselves. In this paper, we proposed a system-level power estimation framework. Users can use their custom power model, and add power estimation automatically. The proposed framework separates the SystemC simulation environment and power estimation into two independent procedures. First, we generate a data collection SystemC module automatically based on the parameters set up by users. This data collection module will automatically collect the information of parameters from SystemC simulation environment, and send these information to power estimation program. Power estimation program will calculate power consumption according to these parameters and formulas set by user. Users can add power estimation to their SystemC simulation environment quickly and use our framework to analysis the power consumption of their SOC system to find improvement issues. Users can use of our framework to compare and analyze various low-power design methods. In this paper, we applied our framework to estimate the power consumption of a 3D graphics SOC to authenticate the functional and practical ability of our framework.

The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system¡¦s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system¡¦s power consumption and improve the system¡¦s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.