In recent years, the miniaturization of cell phones and computers has led to a requirement for antennas to be small and lightweight. Antennas, desired to operate in the WLAN frequency range, often possess physical sizes that are too large for integration with radio-frequency (RF) devices. When integrating antennas into three-dimensional (3D) system-on-package (SOP) transceivers, the maintenance of a compact size also provides isolation from other devices, hence, surface wave propagation or high dielectric constant materials such as low temperature cofired ceramics (LTCC) does not affect nearby components of the transceiver such as filters, baluns, and other embedded passives. Therefore, the application of design methods is necessary for realizing compact antennas in the wireless community that can be integrated to RF packages. Furthermore, it is essential that these compact antennas maintain acceptable performance characteristics, such as impedance bandwidth, low cross-polarization, and high efficiency. In addition, the analysis of circuit modeling techniques that could be used to obtain a better understanding of the physical phenomena of the antenna is quite necessary as modules become more and more complex. Based on these requirements, the focus of this research is to improve the design of compact antennas for wireless communications, wireless local area networks (WLAN), and millimeter-wave applications by using time-domain electromagnetic and circuit modeling techniques and optimizations. These compact antenna designs are applied to practical wireless communications systems such as global system of mobile communications (GSM), Bluetooth Industrial-Scientific-Medical (ISM) devices, IEEE802.11a WLAN, and Local Multipoint Distribution Systems (LMDS) applications. Parametric analyses are conducted to study critical parameters that may affect the antenna designs. Moreover, optimizations are performed to optimize the structures, and measured results are presented to validate design techniques.

Bandpass filters are an essential component of wireless communication systems that only transmits frequencies corresponding to the communication band and rejects all other frequencies. As the deployment of 5G draws nearer, first deployments are expected in 2020 [1], the need for viable filters at the new frequency bands becomes more imminent. Size and performance are two critical considerations for a filter that will be used in emerging mobile communication applications. The high frequency of 5G communication, 28 GHz as opposed to sub 6 GHz for nearly all previous communication protocols, means that previously utilized lumped component based solutions cannot be implemented since they are ill-suited for mm-wave applications. The focus of this work is the miniaturization of a high-performance filter. The Substrate Integrated Waveguide (SIW) is a high performance and promising structure and Low Temperature Co-Fired Ceramic (LTCC) is a high-performance material that both can operate at higher frequencies than the technologies used for previous telecommunication generations. To miniaturize the structure, a compact folded four-cavity SIW filter is designed, implemented and tested. The feeding structure is integrated into the filter to exploit the System on Package (SoP) attributes of LTCC and further reduce the total area of the filter individually and holistically when looking at the final integrated system. Two unique three dimensional (3D) integrated SoP LTCC two-stage SIW single cavity filters and one unique four-cavity filter all with embedded planar resonators are designed, fabricated and tested. The embedded resonators create a two-stage effect in a single cavity filter. The better single cavity design provides a 15% fractional bandwidth at a center frequency of 28.12 GHz, and with an insertion loss of -0.53 dB. The fabricated four-cavity filter has a 3-dB bandwidth of .98GHz centered at 27.465 GHz, and with an insertion loss of -2.66 dB. The designs presented highlight some of the previously leveraged advantages of SoP designs while also including additions of embedded planar resonators to feed the SIW cavity. The integration of both elements realizes a compact and high-performance filter that is well suited for future mm-wave applications including 5G.

The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems. A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed. The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.

The investigation of liquid crystal polymer (LCP) technology to function as a low-cost next-generation organic platform for designs up to millimeter-wave frequencies has been performed. Prior to this research, the electrical performance of LCP had been characterized only with the implementation of standard transmission lines and resonators. In this research, a wide variety of passive functions have been developed on LCP technology and characterized for the first time. Specifically, we present the development of patch antenna arrays for remote sensing applications, the performance of compact low-pass and band-pass filters up to millimeter-wave frequencies, and the integration of passive elements for X-band and V-band transceiver systems. First, dual-frequency/dual-polarization antenna arrays have been developed on multilayer LCP technology and have been integrated with micro-electro-mechanical-system (MEMS) switches to achieve real-time polarization reconfigurability. These arrays are conformal, efficient and have all the features desirable for applications that require space deployment. Second, a wide variety of filters with different physical and functional characteristics have been implemented on both single and multilayer LCP technology. These filters can be classified based on the filter type (low-pass/band-pass), the resonators used (single-mode/dual-mode), the response characteristics (symmetric/asymmetric), and the structure of the filter (modular/non-modular). Last, examples of integrated modules for use in transceiver systems are presented. This part of the research involves the development of duplexers, radiating elements, as well as their integration. The duplexers themselves are realized by integrating a set of band-pass filters and matching networks. The characterization of the individual components, and of the integrated system are included. This research has resulted in a thorough understanding of LCP's electrical performance and its multilayer lamination capabilities pertaining to its functioning as a material platform for integrated microwave systems. Novel passive prototypes that can take advantage of such multilayer capabilities have been developed.

The objective of the proposed research is to present a compact system-on-package (SOP)-based passive front-end solution for millimeter-wave wireless communication/sensor applications, that consists of fully integrated three dimensional (3D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication and testing of V-band transceiver front-end modules using multilayer low temperature co-fired (LTCC) technology. The millimeter-wave front-end module is the foundation of 60 GHz (V-band) wireless systems for short-range multimedia applications, such as high-speed internet access, video streaming and content download. Its integration poses stringent challenges in terms of high performance, large number of embedded passive components, low power consumption, low interference between integrated components and compactness. To overcome these major challenges, a high level of integration of embedded passive functions using low-cost and high-performance materials that can be laminated in 3D, such as the multilayer LTCC, is significantly critical in the module-level design. In this work, various compact and high-performance passive building blocks have been developed in both microstrip and cavity configurations and their integration, enabling a complete passives integration solution for 3D low-cost wireless millimeter-wave front-end modules. It is worthy to note that most of the designs implemented comes away with novel ideas and is presented as the first extensive state-of-art components, entirely validated by measured data at 60 GHz bands.

The goal of the research in this dissertation is to design and characterize embedded passive components, interconnects, and circuits in inhomogeneous, multi-layer liquid crystalline polymer (LCP) substrates. The attenuation properties of inhomogeneous multi-layer LCP substrates were extracted up to 40 GHz. This is the first result for an inhomogeneous LCP stack-up that has been reported. The characterization results show excellent loss characteristics, much better than FR-4-based technology, and they are similar to LTCC and homogeneous LCP-based technology. A two-port characterization method based on measurements of multiple arrays of vias is proposed. The method overcomes the drawbacks of the one-port and other two-port characterizations. Model-to-hardware correlation was verified using multi-layer model in Agilent ADS and measurement-based via model using arrays of the vias. The resulting correlations show that this method can be readily applied to other vertical interconnect structures besides via structures. Comprehensive characterizations have been conducted for the efficient 3D integration of high-Q passives using a balanced LCP substrate. At two different locations from three different large M-LCP panels, 76 inductors and 16 3D capacitors were designed and measured. The parameters for the measurement-based inductor model were extracted from the measured results. The results validate the large panel process of the M-LCP substrate. To reduce the lateral size, multi-layer 3D capacitors were designed. The designed 3D capacitors with inductors can provide optimized solutions for more efficient RF front-end module integration. In addition, the parameters for the measurement-based capacitor model were extracted. Various RF front-end modules have been designed and implemented using high-Q embedded passive components in inhomogeneous multi-layer LCP substrates. A C-band filter using lumped elements has been designed and measured. The lumped baluns were used to design a double balnced-mixer for 5 GHz WLAN application and a doubly double-balanced mixer for 1.78 GHz CDMA receiver miniaturization. Finally, to overcome the limitations of the lumped component circuits, a 30 GHz gap-coupled band-pass filter in inhomogeneous multi-layer LCP substrates, and the measured results using SOLT and TRL calibrations have been compared to the simulation results.

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isolation, and intra and inter-chip communication. Significant research effort spanning many decades has been expended on traditional VLSI integration technologies, encompassing process, circuit and architectural issues to tackle these problems. Recently however, three- dimensional (3-D) integration has emerged as a leading contender in the challenge to meet performance, heterogeneous integration, cost, and size demands through this decade and beyond. Through silicon via (TSV) based 3-D wafer-level integration is an emerging vertical interconnect methodology that is used to route the signal and power supply links through all chips in the stack vertically. Delay and signal integrity (SI) calculation for signal propagation through TSVs is a critical analysis step in the physical design of such systems. In order to reduce design time and mirror well established practices, it is desirable to carry this out in two stages, with the physical structures being modelled by parasitic parameters in equivalent circuits, and subsequent analysis of the equivalent circuits for the desired metric. This thesis addresses both these issues. Parasitic parameter extraction is carried out using a field solver to explore trends in typical technologies to gain an insight into the variation of resistive, capacitive and inductive parasitics including coupling effects. A set of novel closed-form equations are proposed for TSV parasitics in terms of physical dimensions and material properties, allowing the electrical modelling of TSV bundles without the need for computationally expensive field-solvers. Suitable equivalent circuits including capacitive and inductive coupling are derived, and comparisons with field solver provided values are used to show the accuracy of the proposed parasitic parameter models for the purpose of performance and SI analysis. The deep submicron era saw the interconnection delay rather than the gate delay become the major bottleneck in modern digital design. The nature of this problem in 3-D circuits is studied in detail in this thesis. The ubiquitous technique of repeater insertion for reducing propagation delay and signal degradation is examined for TSVs, and suitable strategies and analysis techniques are proposed. Further, a minimal power smart repeater suitable for global on-chip interconnects, which has the potential to reduce power consumption by as much as 20% with respect to a traditional inverter is proposed. A modeling and analysis methodology is also proposed, that makes the smart repeater easier to amalgamate in CAD flows at different levels of hierarchy from initial signal planning to detailed place and route when compared to alternatives proposed in the literature. Finally, the topic of system-level performance estimation for massively integrated systems is discussed. As designers are presented with an extra spatial dimension in 3-D integration, the complexity of the layout and the architectural trade-offs also increase. Therefore, to obtain a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. This thesis presents a cohesive analysis of the technological, cost, and performance trade-offs for digital and mixed-mode systems, outlining the choices available at different points in the design and their ramifications / QC 20100916

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best ways to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This research explores new computer-aided design algorithms for developing optoelectronic systems. These algorithms focus on place and route problems using optical interconnections covering system-on-a-chip design as well as system-on-a-package design. In order to design optoelectronic systems, optical interconnection models are developed at first. The CAD algorithms include optical interconnection models and solve place and route problems for optoelectronic systems. The MCNC and GSRC benchmark circuits are used to evaluate these algorithms.