Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfiguration (DPR) possible. DPR allows a part or parts of a circuit to be reconfigured at run-time, without interrupting the rest of the chip’s operation. As a result, hardware resources can be more efficiently exploited since the chip resources can be reused by swapping in or out hardware tasks to or from the chip in a time-multiplexed fashion. In addition, DPR improves fault tolerance against transient errors and permanent damage, such as Single Event Upsets (SEUs) can be mitigated by reconfiguring the FPGA to avoid error accumulation. Furthermore, power and heat can be reduced by removing finished or idle tasks from the chip. For all these reasons above, DPR has significantly promoted Reconfigurable Computing (RC) and has become a very hot topic. However, since hardware integration is increasing at an exponential rate, and applications are becoming more complex with the growth of user demands, highlevel application design and low-level hardware implementation are increasingly separated and layered. As a consequence, users can obtain little advantage from DPR without the support of system-level middleware. To bridge the gap between the high-level application and the low-level hardware implementation, this thesis presents the important contributions towards a Reliable, Reconfigurable and Real-Time Operating System (R3TOS), which facilitates the user exploitation of DPR from the application level, by managing the complex hardware in the background. In R3TOS, hardware tasks behave just like software tasks, which can be created, scheduled, and mapped to different computing resources on the fly. The novel contributions of this work are: 1) a novel implementation of an efficient task scheduler and allocator; 2) implementation of a novel real-time scheduling algorithm (FAEDF) and two efficacious allocating algorithms (EAC and EVC), which schedule tasks in real-time and circumvent emerging faults while maintaining more compact empty areas. 3) Design and implementation of a faulttolerant microprocessor by harnessing the existing FPGA resources, such as Error Correction Code (ECC) and configuration primitives. 4) A novel symmetric multiprocessing (SMP)-based architectures that supports shared memory programing interface. 5) Two demonstrations of the integrated system, including a) the K-Nearest Neighbour classifier, which is a non-parametric classification algorithm widely used in various fields of data mining; and b) pairwise sequence alignment, namely the Smith Waterman algorithm, used for identifying similarities between two biological sequences. R3TOS gives considerably higher flexibility to support scalable multi-user, multitasking applications, whereby resources can be dynamically managed in respect of user requirements and hardware availability. Benefiting from this, not only the hardware resources can be more efficiently used, but also the system performance can be significantly increased. Results show that the scheduling and allocating efficiencies have been improved up to 2x, and the overall system performance is further improved by ~2.5x. Future work includes the development of Network on Chip (NoC), which is expected to further increase the communication throughput; as well as the standardization and automation of our system design, which will be carried out in line with the enablement of other high-level synthesis tools, to allow application developers to benefit from the system in a more efficient manner.

<p>Modern semiconductor design methods makes it possible to design increasingly complex system-on-a-chips (SOCs). Testing such SOCs becomes highly expensive due to the rapidly increasing test data volumes with longer test times as a result. Several approaches exist to compress the test stimuli and where hardware is added for decompression. This master’s thesis presents a test data compression method based on a modified facsimile code. An embedded processor on the SOC is used to decompress and apply the data to the cores of the SOC. The use of already existing hardware reduces the need of additional hardware. </p><p>Test data may be rearranged in some manners which will affect the compression ratio. Several modifications are discussed and tested. To be realistic a decompressing algorithm has to be able to run on a system with limited resources. With an assembler implementation it is shown that the proposed method can be effectively realized in such environments. Experimental results where the proposed method is applied to benchmark circuits show that the method compares well with similar methods. </p><p>A method of including the response vector is also presented. This approach makes it possible to abort a test as soon as an error is discovered, still compressing the data used. To correctly compare the test response with the expected one the data needs to include don’t care bits. The technique uses a mask vector to mark the don’t care bits. The test vector, response vector and mask vector is merged in four different ways to find the most optimal way.</p>

In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.

Modern semiconductor design methods makes it possible to design increasingly complex system-on-a-chips (SOCs). Testing such SOCs becomes highly expensive due to the rapidly increasing test data volumes with longer test times as a result. Several approaches exist to compress the test stimuli and where hardware is added for decompression. This master’s thesis presents a test data compression method based on a modified facsimile code. An embedded processor on the SOC is used to decompress and apply the data to the cores of the SOC. The use of already existing hardware reduces the need of additional hardware. Test data may be rearranged in some manners which will affect the compression ratio. Several modifications are discussed and tested. To be realistic a decompressing algorithm has to be able to run on a system with limited resources. With an assembler implementation it is shown that the proposed method can be effectively realized in such environments. Experimental results where the proposed method is applied to benchmark circuits show that the method compares well with similar methods. A method of including the response vector is also presented. This approach makes it possible to abort a test as soon as an error is discovered, still compressing the data used. To correctly compare the test response with the expected one the data needs to include don’t care bits. The technique uses a mask vector to mark the don’t care bits. The test vector, response vector and mask vector is merged in four different ways to find the most optimal way.

本研究探討台灣IC設計業者與FAB廠間技術知識連結之影響，主要的研究問題包括：(1)IC設計業者內部技術知識連結與知識流通之影響？(2)技術知識特性與IC設計業者跟FAB廠技術知識連結之影響？(3)IC設計業者跟FAB廠技術知識連結與知識流通之影響？ 本研究採個案研究法，共訪問六家IC設計業者及兩家FAB廠，主要的研究結論如下： 壹、IC設計業者內部技術知識連結對其知識流通之影響 一、本研究發現當專案組織結構的不同，IC設計業者知識的蓄積有所不同。 當專案組織結構採重量型團隊時，IC設計業者主要將知識蓄積在人員身上，例如：個案A公司、個案C公司、個案F公司。 當專案組織結構採自主性團隊時，IC設計業者除了主要將知識蓄積在人員身上外，還將知識蓄積在文件上，例如：個案B公司、個案D公司、個案E公司。 二、本研究發現當團隊成員解決問題透過面對面(包括正式或非正式)溝通方式、分享經驗，有助於IC設計業者知識在共同化過程中創造，例如：個案A公司、個案B公司、個案C公司、個案D公司、個案E公司。 貳、技術知識特性對其IC設計業者跟FAB廠技術知識連結之影響 一、本研究發現當技術知識路徑相依度不同之產品開發專案，IC設計業者與FAB廠間之互動方式有所不同。 當技術知識路徑相依度低之產品開發專案，IC設計業者與FAB廠間的互動方式採共同開發模式，例如：個案A公司、個案D公司、個案E公司。當技術知識路徑相依度高之產品開發專案，IC設計業者與FAB廠間的互動方式採早期投入模式，例如：個案B公司、個案C公司、個案F公司。 二、本研究發現當技術知識路徑相依度不同之產品開發專案，IC設計業者對FAB廠服務經驗的要求有所不同。 當技術知識路徑相依度低之產品開發專案，IC設計業者對FAB廠服務經驗的要求高，例如：個案A公司、個案D公司、個案E公司。 當技術知識路徑相依度高之產品開發專案，IC設計業者對FAB廠服務經驗的要求低，例如：個案B公司、個案C公司、個案F公司。 三、技術知識路徑相依度不同之產品開發專案，不會影響IC設計業者在設計初期搭便車搭便車(Shuttle Bus)，其在驗證最新的設計，例如：個案A公司、個案B公司、個案C公司、個案D公司、個案E公司。 四、本研究發現當技術路徑相依度不同之產品開發專案，IC設計業者與FAB廠間良率管理有所不同。 當技術知識路徑相依度低之產品開發專案，IC設計業者與FAB廠間採系統式良率管理，例如：個案A公司、個案D公司。 當技術知識路徑相依度高之產品開發專案，IC設計業者與FAB廠間採隨機式良率管理，例如：個案B公司、個案C公司、個案E公司、個案F公司。E公司由於只是採成熟的製程技術，技術複雜度不高，而且良率比較高，所以不需要系統式的良率管理。 參、IC設計業者跟FAB廠技術知識連結對其知識流通之影響 一、本研究發現當FAB廠提供豐富的服務經驗時，有助於IC設計業者技術知識的創造上有效的整合，例如：個案A公司、個案B公司、個案C公司、個案D公司、個案E公司、個案F公司。 二、本研究發現當IC設計業者在設計初期時搭便車(Shuttle Bus)時，有助於IC設計業者建立知識創造上的原型，例如：個案A公司、個案B公司、個案C公司、個案D公司、個案E公司。 三、本研究發現當IC設計業者與FAB廠間良率管理採系統式時，有助於IC設計業者知識的吸收上培養跨越疆界者，例如：個案A公司、個案D公司。