A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefore significantly lower than expected, with a SNR of about 39dB but can be expected to be better in a closed-loop simulation. The power consumption of the implemented modules is 0.43mW. However, this is without several modules which were implemented as ideal.

Energy efficiency in embedded processors is of major importance in order to achieve longer operating time for battery operated devices. In this thesis the energy efficiency of a microcontroller based on the open source ZPU microprocessor is evaluated and improved. The ZPU microprocessor is a zero-operand stack machine originally designed for small size FPGA implementation, but in this thesis the core is synthesized for implementation with a 180nm technology library. Power estimation of the design is done both before and after synthesis in the design flow, and it is shown that power estimates based on RTL simulations (before synthesis) are 35x faster to obtain than power estimates based on gate-level simulations (after synthesis). The RTL estimates deviate from the gate-level estimates by only 15% and can provide faster design cycle iterations without sacrificing too much accuracy. The energy consumption of the ZPU microcontroller is reduced by implementing clock gating in the ZPU core and also implementing a tiny stack cache to reduce stack activity energy consumption. The result of these improvements show a 46% reduction in average power consumption. The ZPU architecture is also compared to the more common MIPS architecture, and the Plasma CPU of MIPS architecture is synthesized and simulated to serve as comparison to the ZPU microcontroller. The results of the comparison with the MIPS architecture shows that the ZPU needs on average 15x as many cycles and 3x as many memory accesses to complete the benchmark programs as the MIPS does.

Today Lithium Ion batteries are extensively used in all kinds of electronic equipment due to its superior properties. However, Lithium Ion batteries need to have all the individual cells monitored to ensure the safety and long life time. This master thesis' objective is to design a managing system for a ten cell Lithium Ion battery with an Atmel AVR microcontroller. The main challenge was to scale down the high voltage level a 10 cell battery has and still maintain accuracy when reading this voltage with the AVR. This was solved by using current sense monitors which can handle large common mode voltages. Hardware was made to show proof of concept. It was found that the scaling circuitry had an accuracy of 46mV. In competition with other single chip devices, some other methods have to be found. The design in this thesis is physically too large and too expensive to be of any commercial use. However some other methods worth looking into have been proposed in the last chapter.

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.

Power consumption becomes more important as more devices becomes embedded or battery dependant. Multipliers are generally complex circuits, consuming a lot of energy. This thesis uses Sand's multiplier generator, made for his master thesis, as a basis. It uses tree structures to perform the multiplication, but does not take power consumption into account when generating a multiplier. By adding power optimization to the generator, multipliers with low energy consumption could be made automatically. This thesis adds different reduction tree algorithms (Wallace, Dadda and Reduced Area) to the program, and an optimal algorithm might be found. After the multiplier tree generation, an optimization step is performed, trying to exploit the delay and activity characteristics of the generated multiplier. A simplified version of Oskuii's algorithm is used. To be able to compare the different algorithms with each other, a pre-layout power estimation routine was implemented. The estimator is also used by the post-generation optimization. Since accuracy is important in an estimator, the delay through a multiplier was also investigated. Taking the previous mentioned steps into account, we are able to get a 10% decrease in overall power reduction in a 0,18/0,15um CMOS technology, reported by "IC Compiler". Delay characteristics of a multiplier is also supplied, and can be used by other power estimators. This thesis shows how to achieve less power consumption in multipliers. It also shows that the delay model is important for estimation purposes, and how an estimator is used to optimize a multiplier. The findings in this thesis can be used as is, or be used as a basis for further study.

In this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications running on an embedded processor and reconfigurable accelerator hardware in form of a Xilinx Virtex device. As a start the link was broken down into hardware and software components based on constraints from earlier work and a general literature search. A register architecture for reconfigurable modules, a reconfigurable interface and a backend bridge linking reconfigurable hardware with the system bus were identified as the main hardware components whereas device drivers and a hardware operating system were identified as software components. These components were developed in a bottom-up approach, then deployed, tested and evaluated. Synthesis and simulation results from this thesis suggest that a hybrid register architecture, a mix of shift based and addressable register architecture might be a good solution for a reconfigurable module. Such an architecture enables a reconfigurable interface with full duplex capability with an initially small area overhead compared to a full scale RAM implementation. Although the hybrid architecture might not be very suitable for all types of reconfigurable modules it can be a nice compromise when attempting to achieve a uniform reconfigurable interface. Backend bridge solutions were developed assuming the above hybrid reconfigurable interface. Three main types were researched: a software register backend, a data cache backend and an instruction and data cache backend. Performance evaluation shows that the instruction and data cache outperforms the other two with an average acceleration ratio of roughly 5-10. Surprisingly the data cache backend performs worst of all due to latency ratios and design choices. Aside from the BRAM component required for the cache backends, resource consumption was shown to be only marginally larger than a traditional software register solution. Caching using a controller in the backend-bridge can thus provide good speedup for little cost as far as BRAM resources are not scarce. A software-to-hardware interface has been created has been created through Linux character device driver and a hardware operating system daemon. While the device drivers provide a middleware layer for hardware access the HWOS separates applications from system management through a message queue interface. Performance testing shows a large increase in delay when involving the Linux device drivers and the HWOS as compared to calls directly from the kernel. Although this is natural, the software components are very important when providing a high performance platform. As additional work specialized cell handling for reconfigurable modules has been addressed in the context of a MPEG-4 decoder. Some light has also been shed on design of reconfigurable modules in Xilinx ISE which can radically improve development time and decrease complexity compared to a Xilinx Platform Studio flow. In the process of demonstrating run time reconfigurations it was discovered that a clock signal will resist being piped through bus macros. Also broken functionality has been shown when applying run time reconfiguration to synchronous designs using the framework for self reconfiguration.

In this thesis, methodology for partial self-reconfiguration of synchronous modules has been developed. A simple software-based scheduler has been built for scheduling synchronous modules on the FPGA. The motivation behind this was that partial reconfiguration of synchronous modules at run-time had not been performed earlier in the AHEAD-project. Also, the project report written by the same author as this thesis has shown that a synchronous module can be replaced in a bitfile. However, the project report did not perform this reconfiguration at run-time.Based on the project report, the problem has been decomposed and simple tests using clocked flip-flop designs have been performed on the FPGA. These tests forms a proof-of-concept for partial self-reconfiguration of synchronous modules on the Virtex-4 FPGA. However, the tests also showed that the reconfiguration time was quite high. It took several seconds to write one partial bitstream to the configuration memory.Vegard Endresen has previously made a backend module for data transfer between the HWOS and a reconfigurable module. Experiments were performed in this thesis to see if the clocking methodology could be integrated into this backend module. The module could be built with the methodology, but a running solution on the FPGA was not shown.The software part of the HWOS was rewritten from scratch as the previous version was not thoroughly analyzed. A round-robin scheduler using priority queues has been implemented. A test-driven development technique has been used for development, hopefully making the system more robust. The scheduler is a part of a daemon running on the embedded system, where a message server handles requests for new processes and a placer places new tasks on the FPGA. The complete system was initially based on ideas and code developed by Sverre Hamre and Vegard Endresen in previous AHEAD-projects.

<p>Syftet med arbetet har varit att undersöka om en viss arkitektur kan användas för att underlätta utvecklingen av ett Back Office-system till ett befintligt och komplext verksamhetssystem.</p><p>För att gränsa av arbetet och hitta de delar som var intressanta att fokusera på genomfördes intervjuer med tre olika personer som hade olika syn på ett Back Office-system genom sin yrkesroll. Intervjuerna resulterade i ett antal önskemål för vad man ville uppnå med ett Back Office-system.</p><p>Arbetet resulterade i en arkitektur som kan användas för att underlätta utvecklingen av ett Back Office-system till det befintliga verksamhetssystemet samt till verksamhetssystemet självt. Arkitekturen har utvärderats genom att man först ställde en mängd krav på den och sedan studerade hur den klarade av en mängd nya krav som delvis var relaterade till de gamla kraven.</p><p>Alla tester som gjorts visar på att arkitekturen är väl designad och lätt att underhålla samt att den kommer underlätta den fortsatta utvecklingen av verksamhetssystemet och dess Back Office-system.</p> / <p>The purpose of this thesis has been to evaluate if an architecture could ease the development of a back office system for a present and complex business management system.</p><p>To find the most valuable parts of the system three interviews was conducted. Three different people with different interests in the system were interviewed. The result was a couple of requirements for the back office system.</p><p>The work resulted in an architecture that can ease the development of the back office system and for the business management system itself. The architecture was developed with a first set of requirements that originated from the interviews. Then the architecture was presented with a new set of requirements, also originated from the interviews, and the process of adapting the architecture to the new set of requirements was studied to see if the architecture will be easy to maintain.</p><p>All conducted test shows that the architecture is well designed and easy to maintain. They also show that the architecture will ease further development of the business management system and its back office system.</p>

<p>Medius är ett IT-företag som hjälper företag att effektivisera sina processer med hjälp av IT. För att kunna konkurrera med andra företag och få nya kunder krävs ständigt ny utveckling. Uppdraget med detta examensarbete var att hitta lösningar till ett nytt användargränssnitt för produkten Medius Flow. Vi valde att göra detta med metoden användbarhetsdesign som vi har anpassat för våra egna förutsättningar och mål. Med användbarhet menas att ett system är effektivt att använda, ändamålsenligt och lätt att lära. Detta erhölls genom att ta med användarna i utvecklingen genom fältstudier, diskussioner och tester. Arbetet gick vidare med framtagning av prototyper med efterföljande utvärderingar. För att till slut få fram ett designförslag. Med tanke på utvärderingar och våra egna åsikter är vi nöjda med resultatet som t.ex. innehöll en större arbetsyta, mer effektiv navigering och ett modernare utseende. Det som återstår för Medius är nu att implementera de lösningar vi har föreslagit.</p> / <p>Medius is an IT company who helps other companies to make their processes more efficient. To be able to compete with other companies and to get new costumers, constant development is required. The assignment of this final thesis was to find solutions to a new user interface for the product Medius Flow. We chose to do this with a method called Usability Design, which we adapted to our own conditions and goals. The meaning of usability is that a system is efficient to use, suited to the purpose and easy to learn. This was accomplished by letting the users help with the development through field studies, discussions and tests. The work went on with prototypes, followed by evaluations, to finally get a design proposal. With the evaluations and our own opinions in mind, we are satisfied with the result which for example included a larger working area, more efficient navigation and a more modern appearance. The remaining part for Medius is now to implement the solutions we suggested.</p>

Medius är ett IT-företag som hjälper företag att effektivisera sina processer med hjälp av IT. För att kunna konkurrera med andra företag och få nya kunder krävs ständigt ny utveckling. Uppdraget med detta examensarbete var att hitta lösningar till ett nytt användargränssnitt för produkten Medius Flow. Vi valde att göra detta med metoden användbarhetsdesign som vi har anpassat för våra egna förutsättningar och mål. Med användbarhet menas att ett system är effektivt att använda, ändamålsenligt och lätt att lära. Detta erhölls genom att ta med användarna i utvecklingen genom fältstudier, diskussioner och tester. Arbetet gick vidare med framtagning av prototyper med efterföljande utvärderingar. För att till slut få fram ett designförslag. Med tanke på utvärderingar och våra egna åsikter är vi nöjda med resultatet som t.ex. innehöll en större arbetsyta, mer effektiv navigering och ett modernare utseende. Det som återstår för Medius är nu att implementera de lösningar vi har föreslagit. / Medius is an IT company who helps other companies to make their processes more efficient. To be able to compete with other companies and to get new costumers, constant development is required. The assignment of this final thesis was to find solutions to a new user interface for the product Medius Flow. We chose to do this with a method called Usability Design, which we adapted to our own conditions and goals. The meaning of usability is that a system is efficient to use, suited to the purpose and easy to learn. This was accomplished by letting the users help with the development through field studies, discussions and tests. The work went on with prototypes, followed by evaluations, to finally get a design proposal. With the evaluations and our own opinions in mind, we are satisfied with the result which for example included a larger working area, more efficient navigation and a more modern appearance. The remaining part for Medius is now to implement the solutions we suggested.