Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

Thesis (Ph.D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 141 pages. Includes vita. Includes bibliographical references.

Thesis (M.Phil.) - University of Queensland, 2006. / Includes bibliography.

Thesis (Ph. D.)--Ohio State University, 2005. / Available online via OhioLINK's ETD Center; full text release delayed at author's request until 2006 Jul 29.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 76-84).

Heterogeneous System-on-Chip (SoC) architectures combine general-purpose processors with many accelerators, which are application-specific computing engines. By having their hardware optimized to perform specific tasks, accelerators deliver massive speedups and energy savings compared to corresponding software executions on a processor. Heterogeneity and hardware specialization complicate accelerator design and integration, reducing regularity and reusability across platforms. The many system-level architectural aspects to consider make it hard to explore the design space and arrive to optimal solutions. Furthermore, integrating accelerators affects the programmability of the applications and the security of the entire SoC. In this dissertation, I present design methodologies and architectural contributions that use multi-functional interfaces to simplify many of the tasks that designers perform when designing and integrating accelerators in heterogeneous SoCs. The accelerator interfaces exploit latency-insensitive design to effectively explore the design space when multiple accelerators are integrated and to speed up the verification of accelerators. This improves their reusability across SoC platforms, while ensuring correctness when the accelerators are integrated with the various components of the SoC. In addition, the accelerator interfaces improve the integration with software by making it transparent and by establishing a strong layer of protection between accelerators and applications.The interfaces aim at securing the accelerators and the applications without requiring modifications to the accelerator implementations and without degrading their performance and energy efficiency.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Consumers demand new and innovative personal computing devices every 2 years when their cellular phone service contracts are renewed. Yet, a 2 year development cycle for the concurrent development of both hardware and software is nearly impossible. As more components and features are added to the devices, maintaining this 2 year cycle with current tools will become commensurately harder. This dissertation delves into the feasibility of simplifying the development of such systems by employing heterogeneous systems on a chip in conjunction with a retargetable compiler such as the hybrid computer retargetable compiler (Hy-C). An example of a simple architecture description of sufficient detail for use with a retargetable compiler like Hy-C is provided. As a software engineer with 30 years of experience, I have witnessed numerous system failures. A plethora of software development paradigms and tools have been employed to prevent software errors, but none have been completely successful. Much discussion centers on software development in the military contracting market, as that is my background. The dissertation reviews those tools, as well as some existing retargetable compilers, in an attempt to determine how those errors occurred and how a system like Hy-C could assist in reducing future software errors. In the end, the potential for a simple retargetable solution like Hy-C is shown to be very simple, yet powerful enough to provide a very capable product in a very fast-growing market.

Finally, the PSRR performance of LDO is studied. An energy-efficient embedded ripple feed-forward path is proposed to improve the PSRR of LDO. Comparing with some state-of-the-art techniques for PSRR improvement, the proposed LDO features very simple structure thus low-power consumption. A LDO implemented in 0.18-mum CMOS technology with 0.042-mm2 active area has been designed to verify the idea. With an external 4.7-muF output capacitor, in the maximum load condition (i.e. at 25 mA), the PSRR is -77 dB at 1 MHz, -85 dB at 2.5 MHz and -55 dB at 5 MHz, respectively. The quiescent current is 15 muA only, while the transient voltage overshoot or undershoot is less than 40 mV when load current changes between 1 mA and 25 mA with 40-ns step time. The LDO achieves good line and load regulations of 3 mV/V and 50 muV/mA, respectively. / Remotely- or battery-powered wireless system-on-a-chip (SoC) needs energy-efficient and high-integration power-management solutions due to their energy-aware characteristics. Low-dropout regulator (LDO) is a good solution because of its excellent performances such as low power consumption, fast load-transient response and high power-supply ripple rejection (PSRR). Moreover, it is easy to be fully integrated since no inductor is needed to be the energy-storage element. Recent development of output-capacitorless LDO (OCL-LDO) realizes on-chip, local voltage regulation to enable more effective integrated power management for SoC. In this thesis, OCL-LDOs with low power consumption and fast load-transient response are investigated and presented in this thesis. LDO with output capacitor for high-PSRR operation to provide clean power supply to RF circuits is also reported. Three LDOs are developed and fabricated to verify the proposed ideas. / The first design is an ultra low-power voltage regulator for remotely powered energy-autonomous devices. It has been fabricated in a commercial 0.18-mum CMOS technology and applied to a passive UHF RFID tag IC. With the low-power voltage reference circuit and sub-threshold operations, the total quiescent current is 700 nA under a 1.8-V power supply. The output voltage of the regulator is 1.45 V with load capability of 50 muA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/°C, respectively. A POR signal with 150-ns-width pulse is also generated to reset the digital processing part in the tag IC. / The second design is a fast-transient OCL-LDO, which has been implemented in a commercial 90-nm CMOS technology. Experimental result verifies that it is stable for a capacitive load from 0 to 50 pF and with load capability of 100 rnA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the power transistor promptly. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 mus. While the measured power consumption is only 6 muW under a 0.75-V supply. / Guo, Jianping. / Adviser: Ka Nang Leung. / Source: Dissertation Abstracts International, Volume: 73-06, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Software cognitive radios and Internet of Things (IoT) are recent interest areas that need low loss and low power consumption hardware. More specifically, the area of software cognitive radios requires that hardware be frequency agile and highly selective. Meanwhile, IoT relies on multiple low power sensor networks. By combining Complementary Metal Oxide Semiconductors (CMOS) technology with piezoelectric Micro-Electro-Mechanical Systems (MEMS), we can fabricate Systems-on-Chip (SoC) that can be used as filters or references (oscillators) and highly selective sensors. In this work we developed a die-level compatible process for the monolithic integration of Bulk Acoustic Resonators (BAWs) on CMOS for low power, reduced area and high-quality passives for radio frequency applications. Using CMOS as a fabrication substrate some stringent requirements were added to maintain the dies and the technology’s integrity. A few of these limitations were the need for a low thermal budget fabrication process, die handling and electro-static discharge (ESD) protection. The devices were first fabricated on glass for modeling extraction that was later used for the design of the integrated circuits (IC). Three integrated circuits were designed as substrates for the integration using IBM’s 180nm and TSMC’s 65nm technology. A monolithic BAW oscillator with a resonance frequency of 1.8GHz was demonstrated with an FOM ~186dBc/Hz, comparable to other academia work. Using the developed process, a membrane BAW structure (FBAR) was integrated as well. Using a susceptor coating and zinc oxide’s (ZnO) high temperature coefficient of frequency (TCF) the device was studied as an alternative uncooled infrared sensor. Finally, a reprogrammable IC and an RF PCB were designed for volatile organic compound (VOC) testing using self-assembled monolayers (SAMs) as the absorber layer.