Post-silicon validation has become a critical stage in the system-on-chip (SoC) development cycle, driven by increasing design complexity, higher level of integration and decreasing time-to-market. According to recent reports, post-silicon validation effort comprises more than 50% of the overall development effort of an 65nm SoC. Though post-silicon validation covers many aspects ranging from electronic properties of hardware to performance and power consumption of whole systems, a central task remains validating functional correctness of both hardware and its integration with software. There are several key challenges to achieving accelerated and low-cost post-silicon functional validation. First, there is only limited silicon observability and controllability; second, there is no good test coverage estimation over a silicon device; third, it is difficult to generate good post-silicon tests before a silicon device is available; fourth, there is no effective software robustness testing approaches to ensure the quality of hardware/software integration. We propose a systematic approach to accelerating post-silicon functional validation with virtual prototypes. Post-silicon test coverage is estimated in the pre-silicon stage by evaluating the test cases on the virtual prototypes. Such analysis is first conducted on the initial test suite assembled by the user and subsequently on the expanded test suite which includes test cases that are automatically generated. Based on the coverage statistics of the initial test suite on the virtual prototypes, test cases are automatically generated to improve the test coverage. In the post-silicon stage, our approach supports coverage evaluation of test cases on silicon devices to ensure fidelity of early coverage evaluation. The generated test cases are issued to silicon devices to detect inconsistencies between virtual prototypes and silicon devices using conformance checking. We further extend the test case generation framework to generate and inject fault scenario with virtual prototypes for driver robustness testing. Besides virtual prototype-based fault injection, an automatic driver fault injection approach is developed to support runtime fault generation and injection for driver robustness testing. Since virtual prototype enables early driver development, our automatic driver fault injection approach can be applied to driver testing in both pre-silicon and post-silicon stages. For preliminary evaluation, we have applied our coverage evaluation and test generation to several network adapters and their virtual prototypes. We have conducted coverage analysis for a suite of common tests on both the virtual prototypes and silicon devices. The results show that our approach can estimate the test coverage with high fidelity. Based on the coverage estimation, we have employed our automatic test generation approach to generate additional tests. When the generated test cases were issued to both virtual prototypes and silicon devices, we observed significant coverage improvement. And we detected 20 inconsistencies between virtual prototypes and silicon devices, each of which reveals a virtual prototype or silicon device defect. After we applied virtual prototype-based fault injection approach to virtual prototypes for three widely-used network adapters, we generated and injected thousands of fault scenarios and found 2 driver bugs. For automatic driver fault injection, we have applied our approach to 12 widely used drivers with either virtual prototypes or silicon devices. After testing all these drivers, we found 28 distinct bugs.

As today's real-time embedded systems grow increasingly ubiquitous, rising complexity ensues as more and more functionalities are integrated. Market dynamics and competitiveness further constrict the technology-to-market time requirement, consequently pushing it to the very forefront of consideration during the development process. Traditional system development approaches could no longer efficiently cope with such formidable demands, and a paradigm shift has been perceived by many as a mandate. This thesis presents a novel platform-centric SoC design method that relies on a platform-based design to expedite the overall development process. The proposed approach offers a new perspective towards the complex systems design paradigm, and can attain the desired paradigm shift through extensive reuse and flexibility. It offers a unified communication means for all sectors involved in the development process: Semiconductor vendors can use it to publish their platform specifications; Tool vendors can use it to develop and/or enhance their tools; System developers can use it to efficiently develop the system. Key technologies are also identified, namely the Extensible Markup Language (XML) and the Unified Modeling Language (UML), that realize the proposed approach. This thesis extends XML to attain a standard means for modeling, and processing a large amount of reusable platform-related data. Additionally, it employs UML's own extension mechanism to derive a UML dialect that can be used to model real-time systems and characteristics. This UML dialect, i.e. the UML profile for Codesign Modeling Framework (UML-CMF), remains compliant to the UML standard. A sub-profile within the UML profile for Codesign Modeling Framework is also developed so as to furnish a means for efficient modeling of platforms, and that can be seamlessly integrated with other real-time modeling capabilities offered by the UML-CMF. Such an effort yields a robust UML-compliant language that is suitable for a general platform-based modeling and design. A practical use of the proposed approach is demonstrated through a powerful case study that applies the approach to develop a digital camera system. The results are comparatively presented against the SpecC approach in terms of cost metrics based on the COCOMO II model.

This thesis describes the architecture, verification, qualification, and packaging of a 16-channel silicon-germanium (SiGe) Remote Electronics Unit (REU) designed for use in extreme environment applications encountered on NASA's exploration roadmap. The SiGe REU was targeted for operation outside the protective electronic "vaults" in a lunar environment that exhibits cyclic temperature swings from -180ºC to 120ºC, a total ionizing dose (TID) radiation level of 100 krad, and heavy ion exposure (single event effects) over the mission lifetime. The REU leverages SiGe BiCMOS technological advantages and design methodologies, enabling exceptional extreme environment robustness. It utilizes a mixed-signal Remote Sensor Interface (RSI) ASIC and an HDL-based Remote Digital Control (RDC) architecture to read data from up to 16 sensors using three different analog channel types with customizable gain, current stimulus, calibration, and sample rate with 12-bit analog-to-digital conversion. The SiGe REU exhibits excellent channel sensitivity throughout the temperature range, hardness to at least 100 krad TID exposure, and single event latchup immunity, representing the cutting edge in cold-capable electronic systems. The SiGe REU is the first example within a potential paradigm shift in space-based electronics.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

The work presented in this thesis aims at validating an original multicriteria performances estimation tool, NESSIE, dedicated to the prediction of performances to accelerate the design of electronic embedded systems. <p><p>This tool has been developed in a previous thesis to cope with the limitations of existing design tools and offers a new solution to face the growing complexity of the current applications and electronic platforms and the multiple constraints they are subjected to. <p><p>More precisely, the goal of the tool is to propose a flexible framework targeting embedded systems in a generic way and enable a fast exploration of the design space based on the estimation of user-defined criteria and a joint hierarchical representation of the application and the platform.<p><p>In this context, the purpose of the thesis is to put the original framework NESSIE to the test to analyze if it is indeed useful and able to solve current design problems. Hence, the dissertation presents :<p><p>- A study of the State-of-the-Art related to the existing design tools. I propose a classification of these tools and compare them based on typical criteria. This substantial survey completes the State-of-the-Art done in the previous work. This study shows that the NESSIE framework offers solutions to the limitations of these tools.<p>- The framework of our original mapping tool and its calculation engine. Through this presentation, I highlight the main ingredients of the tool and explain the implemented methodology.<p>- Two external case studies that have been chosen to validate NESSIE and that are the core of the thesis. These case studies propose two different design problems (a reconfigurable processor, ADRES, applied to a matrix multiplication kernel and a 3D stacking MPSoC problem applied to a video decoder) and show the ability of our tool to target different applications and platforms. <p><p>The validation is performed based on the comparison of a multi-criteria estimation of the performances for a significant amount of solutions, between NESSIE and the external design flow. In particular, I discuss the prediction capability of NESSIE and the accuracy of the estimation. <p><p>-The study is completed, for each case study, by a quantification of the modeling time and the design time in both flows, in order to analyze the gain achieved by our tool used upstream from the classical tool chain compared to the existing design flow alone. <p><p><p>The results showed that NESSIE is able to predict with a high degree of accuracy the solutions that are the best candidates for the design in the lower design flows. Moreover, in both case studies, modeled respectively at a low and higher abstraction level, I obtained a significant gain in the design time. <p><p>However, I also identified limitations that impact the modeling time and could prevent an efficient use of the tool for more complex problems. <p><p>To cope with these issues, I end up by proposing several improvements of the framework and give perspectives to further develop the tool. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC).<p>These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises.<p>In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow.<p>In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market.<p>In this context, this thesis presents: <p>- A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction.<p>- The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices.<p>- The implementation of a couple of two new tools of our own:<p>- Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance.<p>-Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis.<p><p>To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature.<p>Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool.<p>We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization.<p>Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benefits are then discussed.<p>We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-07-06T13:04:33Z No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-07-10T14:27:37Z (GMT) No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Made available in DSpace on 2018-07-10T14:37:58Z (GMT). No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) Previous issue date: 2014-03-13 / The increase in the number of cores available in Systems on a Chip has enabled the design of circuits with increasingly aggressive specifications. Efficient interconnection architectures such as intrachip networks are critical to the viability of these projects. However, measuring and comparing performanceof these networks for a given system is still a challenging task, which results from: (i) the complexity imposed by the abundance of available options in the design space of these networks; (ii) the current non-adoption of a unique evaluation platform to compare different networks proposals; (iii) the fact that the network traffic has a greater influence on the performance of such networks than any other design characteristic. This work has as main strategic goal the evaluation and comparison of different intrachip network architectures through the use of a unified evaluation platform. It adopts Nocbench, a recent platform, already validated in some contexts and proposed as a standard for the evaluation of intrachip networks. The employed evaluation method is based on the simulation of networks and uses as input traffic and computation models described in the form of traces, both extracted from real application. The main contributions of this work reside in: (i) the proposal of several enhancements to the chosen platform; (ii) the development of modules added to integrate the networks Hermes HS,Hermes OO, Hermes TB, Hermes VC, and YeaH from the author?s research group to the platform; (iii) the enhancement of the platform performance evaluation process, through the inclusion of metrics usually employed to compare intrachip networks, including: latency, throughput and jitter. A set of experiments validates the contributions and demonstrate the use the Nocbench platform as a useful tool in the comparison of intrachip networks of diverse origins. / O aumento no n?mero de n?cleos presentes em Sistemas Integrados em Chip tem proporcionado o projeto de circuitos com especifica??es cada vez mais agressivas. Arquiteturas de interconex?o eficientes tais como as redes intrachip s?o fundamentais para a viabilidade destes projetos. Entretanto, medir e comparar o desempenho destas redesainda ? uma tarefa desafiadora, resultado: (i) da complexidade imposta pela abund?ncia de op??es dispon?veis no espa?o de projeto destas redes; (ii) da atual n?o ado??o de uma mesma plataforma de avalia??o para a compara??o de diferentes propostas de redes; (iii) e do fato de o tr?fego de rede exercer uma influ?ncia muito maior do que qualquer caracter?stica de projeto no desempenho destas. Este trabalho tem como principal objetivo estrat?gico a avalia??o e compara??o de diferentes arquiteturas de redes intrachip atrav?s de uma plataforma de avalia??o unificada. Adota-se Nocbench, uma plataforma recente, j? validada em alguns contextos e proposta como um padr?o para a avalia??o de redes intrachip. O m?todo de avalia??o empregado baseia-se na simula??o de redes e utiliza como entrada modelos de tr?fego e de computa??o descritos sob a forma de traces, ambos extra?dos de aplica??es reais. As principais contribui??es do trabalho residem: (i) na proposta de diversas melhorias para a plataforma escolhida; (ii) no desenvolvimento de m?dulos para a integra??o das redes Hermes HS, Hermes OO, Hermes TB, Hermes VC e YeaHdo grupo de pesquisa do Autor ? plataforma em quest?o; (iii) no aprimoramento do processo de avalia??o de desempenho da plataforma, atrav?s da inclus?o de m?tricas comumente utilizadas para comparar redes intrachip, incluindo: lat?ncia, vaz?oe jitter. Um conjunto de experimentos valida as contribui??es e demonstra o uso da plataforma Nocbench como uma ferramenta ?til na compara??o de redes intrachip de origens diversas.

Ce mémoire traite des systèmes intégrés sur puce (System-on-Chip) à faible consommation d'énergie tels que ceux qui seront utilisés dans les équipements portables de future génération (ordinateurs de poche (PDA), téléphones mobiles). S'agissant d'équipements alimentés par des batteries, la consommation énergétique est un problème critique. <p><p>Ces plateformes contiendront probablement une douzaine de coeurs de processeur et une quantité importante de mémoire embarquée. Une architecture de communication optimisée sera donc nécessaire afin de les interconnecter de manière efficace. De nombreuses architectures de communication ont été proposées dans la littérature: bus partagés, bus pontés, bus segmentés et plus récemment, les réseaux intégrés (NoC).<p><p>Toutefois, à l'exception des bus, la consommation d'énergie des réseaux d'interconnexion intégrés a été largement ignorée pendant longtemps. Ce n'est que très récemment que les premières études sont apparues dans ce domaine.<p><p>Cette thèse présente:<p><p>- Une analyse complète de l'espace de conception des architectures de communication intégrées. Sur base de cet espace de conception et d'un état de l'art détaillé, des techniques jusqu'alors inexplorées ont pu être identifiées et investiguées. <p>- La conception d'environnements de simulation de bas et haut niveaux permettant de réaliser des comparaisons entre différentes architectures de communication en termes de consommation énergétique et de surface.<p>- La conception et la validation d'une architecture de communication intégrée innovante basée sur le multiplexage spatial<p><p>Ce dernier point a pour ambition de démontrer qu'un réseau basé sur le multiplexage spatial (SDM) constitue une alternative intéressante aux réseaux classiques principalement basés sur le multiplexage temporel dans le contexte très spécifique des architectures de communication intégrées.<p><p>Nous démontrerons la validité de la solution proposée à l'aide de campagnes de simulation de haut niveau pour divers types de trafic ainsi que des simulations de plus bas niveau. L'étude concerne successivement la conception de routers SDM, des interfaces réseau et finalement d'un réseau complet. Les avantages et inconvénients d'une telle technique seront discutés en détails. / Doctorat en sciences appliquées / info:eu-repo/semantics/nonPublished

Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA. / <p>QC 20140609</p>