Ma, Qiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Floorplanning --- p.2 / Chapter 1.3 --- Motivations --- p.4 / Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5 / Chapter 1.5 --- Problem Formulation --- p.8 / Chapter 1.6 --- Progress on the Problem --- p.10 / Chapter 1.7 --- Contributions --- p.12 / Chapter 1.8 --- Thesis Organization --- p.14 / Chapter 2 --- Literature Review on MSV --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16 / Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16 / Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18 / Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19 / Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20 / Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21 / Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22 / Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22 / Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23 / Chapter 2.4 --- Summary --- p.27 / Chapter 3 --- MSV Driven Floorplanning --- p.29 / Chapter 3.1 --- Introduction --- p.29 / Chapter 3.2 --- Problem Formulation --- p.32 / Chapter 3.3 --- Algorithm Overview --- p.33 / Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33 / Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35 / Chapter 3.4.2 --- Proof of Optimality --- p.36 / Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37 / Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38 / Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39 / Chapter 3.5 --- Simulated Annealing --- p.39 / Chapter 3.5.1 --- Moves --- p.39 / Chapter 3.5.2 --- Cost Function --- p.40 / Chapter 3.6 --- Experimental Results --- p.40 / Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45 / Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46 / Chapter 3.7 --- Summary --- p.46 / Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.52 / Chapter 4.3 --- Algorithm Overview --- p.56 / Chapter 4.4 --- Voltage Assignment Problem --- p.56 / Chapter 4.4.1 --- Lagrangian Relaxation --- p.58 / Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60 / Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64 / Chapter 4.4.4 --- Solution Transformation --- p.66 / Chapter 4.5 --- Simulated Annealing --- p.69 / Chapter 4.5.1 --- Moves --- p.69 / Chapter 4.5.2 --- Speeding up heuristic --- p.69 / Chapter 4.5.3 --- Cost Function --- p.70 / Chapter 4.5.4 --- Annealing Schedule --- p.71 / Chapter 4.6 --- Experimental Results --- p.71 / Chapter 4.7 --- Summary --- p.72 / Chapter 5 --- Conclusion --- p.76 / Bibliography --- p.80

Jiang, Li. / "October 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 71-76). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Three Dimensional Integrated Circuit --- p.1 / Chapter 1.1.1 --- 3D ICs --- p.1 / Chapter 1.1.2 --- Manufacture --- p.3 / Chapter 1.2 --- Test Architecture Design and Optimization for SoCs --- p.4 / Chapter 1.2.1 --- Test Wrapper --- p.4 / Chapter 1.2.2 --- Test Access Mechanism --- p.6 / Chapter 1.2.3 --- Test Architecture Optimization and Test Scheduling --- p.7 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 2 --- On Test Time and Routing Cost --- p.12 / Chapter 2.1 --- Introduction --- p.12 / Chapter 2.2 --- Preliminaries and Motivation --- p.13 / Chapter 2.3 --- Problem Formulation --- p.17 / Chapter 2.3.1 --- Test Cost Model --- p.17 / Chapter 2.3.2 --- Routing Model --- p.17 / Chapter 2.3.3 --- Problem Definition --- p.19 / Chapter 2.4 --- Proposed Algorithm --- p.22 / Chapter 2.4.1 --- Outline of The Proposed Algorithm --- p.22 / Chapter 2.4.2 --- SA-Based Core Assignment --- p.24 / Chapter 2.4.3 --- Heuristic-Based TAM Width Allocation --- p.25 / Chapter 2.4.4 --- Fast routing Heuristic --- p.28 / Chapter 2.5 --- Experiments --- p.29 / Chapter 2.5.1 --- Experimental Setup --- p.29 / Chapter 2.5.2 --- Experimental Results --- p.31 / Chapter 2.6 --- Conclusion --- p.34 / Chapter 3 --- Pre-bond-Test-Pin Constrained Test Wire Sharing --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Preliminaries and Motivation --- p.38 / Chapter 3.2.1 --- Prior Work in SoC Testing --- p.38 / Chapter 3.2.2 --- Prior Work in Testing 3D ICs --- p.39 / Chapter 3.2.3 --- Test-Pin-Count Constraint in 3D IC Pre-Bond Testing --- p.40 / Chapter 3.2.4 --- Motivation --- p.41 / Chapter 3.3 --- Problem Formulation --- p.43 / Chapter 3.3.1 --- Test Architecture Design under Pre-Bond Test-Pin-Count Constraint --- p.44 / Chapter 3.3.2 --- Thermal-aware Test Scheduling for Post-Bond Test --- p.45 / Chapter 3.4 --- Layout-Driven Test Architecture Design and Optimization --- p.46 / Chapter 3.4.1 --- Scheme 1: TAM Wire Reuse with Fixed Test Architectures --- p.46 / Chapter 3.4.2 --- Scheme 2: TAM Wire Reuse with Flexible Pre-bond Test Architecture --- p.52 / Chapter 3.5 --- Thermal-Aware Test Scheduling for Post-Bond Test --- p.53 / Chapter 3.5.1 --- Thermal Cost Function --- p.54 / Chapter 3.5.2 --- Test Scheduling Algorithm --- p.55 / Chapter 3.6 --- Experimental Results --- p.56 / Chapter 3.6.1 --- Experimental Setup --- p.56 / Chapter 3.6.2 --- Results and Discussion --- p.58 / Chapter 3.7 --- Conclusion --- p.59 / Chapter 3.8 --- Acknowledgement --- p.60 / Chapter 4 --- Conclusion and Future Work --- p.69 / Bibliography --- p.70

Or, Pui Ying. / "July 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Abstracts in English and Chinese. / Acknowledgments / Table of Content / List of Figures / List of Tables / List of Publications / Chapter Chapter 1 - --- Background of LDO Research / Chapter 1.1 --- Structure of a LDO --- p.1-1 / Chapter 1.2 --- Principle of Operation of LDO --- p.1-2 / Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3 / Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3 / Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4 / Chapter 1.6 --- An Advanced LDO Structure --- p.1-4 / Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5 / References --- p.1-6 / Chapter Chapter 2 - --- PSRR Analysis / Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3 / Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6 / Chapter 2.3 --- Conclusion of Chapter --- p.2-12 / References --- p.2-13 / Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection / Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5 / Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7 / Chapter 3.3 --- Experimental Results --- p.3-15 / Chapter 3.4 --- Conclusion of Chapter --- p.3-21 / References --- p.3-22 / Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique / Chapter 4.1 --- Proposed LDO --- p.4-3 / Chapter 4.2 --- Experimental Results --- p.4-7 / Chapter 4.3 --- Comparison --- p.4-11 / Chapter 4.4 --- Conclusion of Chapter --- p.4-12 / Reference --- p.4-13 / Chapter Chapter 5 - --- Conclusion and Future Work

Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systems-on-Chips (SoCs) interconnect architectures are based on shared-bus communication, which can carry only one communication transaction at a time. This limits the communication bandwidth and scalability. Networks-on-Chip (NoC) were proposed as a promising solution for designing large and complex SoCs. The NoC paradigm provides better scalability and reusability for future SoCs, however, long-distance multi-hop communication through traditional metal wires suffers from both high latency and power consumption. A radical solution to address this challenge is to add long-range, low power, and high-bandwidth single-hop links between distant cores. The use of optical or on-chip RF wireless links has been explored in this context. However, all previous work has focused on regular mesh-based metal wire fabrics that were expanded with one or two additional link types only for long-distance communication. In this thesis we address the following main research questions to address the above-mentioned challenges: (1) What library of different link types would represent an optimum in the design space? (2) How would these links be used to design an application-specific NoC architecture? (3) How would applications use the resulting NoC architecture efficiently? We hypothesize that networks with a higher degree of heterogeneity, i.e., three or more link types, will improve the network throughput and consume less energy compared to traditional NoC architectures. In order to verify our hypothesis and to address the research challenges, we design and analyze optimal heterogeneous networks under different realistic traffic models by considering different cost and performance trade-offs in a comprehensive technology-agnostic simulation framework that uses metaheuristic optimization techniques. As opposed to related work, our heterogeneous links can be placed anywhere in the network, which allows to explore the entire search space. The resulting application-specific networks are then analyzed by using complex network techniques, such as community detection and small-worldness, to understand how heterogeneous link types are used to improve the NoCs performance and cost. Next, we use the application-specific networks as a target architecture for other applications. The goal is to evaluate the performance of our new NoCs for applications they have not been designed for by finding optimal resource allocations. Our results show that there is an optimal number of heterogeneous link types for each set of constraints and that networks with three or more heterogeneous link types provide significantly higher throughput along with lower energy consumption compared to both homogeneous link type and regular 2D mesh networks under three different traffic scenarios. Our evolved networks with three different technology-driven link types, namely metal wires, wireless, and optical links, provide 15% more throughput and fourteen times less energy consumption compared to homogeneous link type network. When ten different abstract link types are used in the design, 12% more throughput and 52% less energy consumption are obtained compared to networks with three different technology-driven link types. This shows that heterogeneous NoC designs based on traditional metal wires, wireless, and optical links, occupy a non-optimal spot in the entire design space. Our results further show that heterogeneous NoCs scale up significantly better in terms of performance and cost compared to mesh networks. We uncovered that network communities evolve robustly and that heterogeneous link types are efficiently establishing inter- and intra-subnet connections depending on their link type properties. We also show that mapping an application on our application-specific NoC architecture provides on average 45% more throughput at 70% less energy consumption compared to regular 2D mesh networks. The NoCs are therefore not only good for the application they were designed for, but for a broad range of other applications as well.

The aggressive evolution of the semiconductor industry smaller process geometries, higher densities, and greater chip complexity has provided design engineers the means to create complex, high-performance System-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge (tens of Mega Bytes) amount of memory, all on the same chip. Dealing with the global on-chip memory allocation/deallocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme which presents a shift in the way designers look at on-chip dynamic memory allocation we present the System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the management of memory allocated to a particular on-chip Processing Element, e.g., an operating systems management of memory allocated to a particular processor). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time. A new tool is introduced to generate a custom optimized version of the SoCDMMU hardware. Also, a real-time operating system is modified support the new proposed SoCDMMU. We show an example where shared memory multiprocessor SoC that employs the Two-Level Memory Management and utilizes the SoCDMMU has an overall average speedup in application transition time as well as normal execution time.

Thesis (M.S.)--State University of New York at Binghamton, Department of Electrical and Computer Engineering. / Includes bibliographical references (p. 55-56).

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (leaves 105-109).

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (leaves 146-149).

The unabated silicon technology scaling makes design and manufacturing increasingly harder in nanometer VLSI. Emerging technologies on the horizon require strong design automation to handle the large complexity of future systems. This dissertation studies eight related research topics in design and manufacturing closure in nanometer VLSI as well as design optimization for emerging technologies from physical synthesis perspective. In physical synthesis for design closure, we study three research topics, which are key challenges in nanometer VLSI designs: (a) We propose a highly efficient floorplanning algorithm to minimize substrate noise for mixed-signal system-on-a-chip designs. (b) We propose a clock tree synthesis algorithm to reduce clock skew under thermal variation. (c) We develop a global router, BoxRouter to enhance routability which is one of the classic but still critical challenges in modern VLSI. In physical synthesis for manufacturing closure, we propose the first systematic manufacturability aware routing framework to address three key manufacturing challenges: (a) We develop a predictive chemical-mechanical polishing model to guide global routing in order to reduce surface topography variation. (b) We formulate a random defect minimize problem in track routing, and develop a highly efficient algorithm. (b) We propose a lithography enhancement technique during detailed routing based on statistical and macro-level Post-OPC printability prediction. Regarding design optimization of emerging technologies, we focus on two topics, one in double patterning technology for future VLSI fabrication and the other in microfluidics for biochips: (a) We claim double patterning should be considered during physical synthesis, and propose an effective double patterning technology aware detailed routing algorithm. (b) We propose a droplet routing algorithm to improve routability in digital microfluidic biochip design. / text