Im Rahmen dieser Arbeit wurden monolithische Halbleiternanostrukturen hinsichtlich neuartiger nanoelektronischer Transporteffekte untersucht. Hierbei wurden gezielt der ballistische Charakter des Ladungstransportes in mesoskopischen Strukturen sowie die kapazitive Kopplung einzelner Strukturbereiche ausgenutzt, um ballistische Verstärkerelemente und logische Gatter zu realisieren. Die untersuchten Nanostrukturen basieren auf dem zweidimensionalen Elektronengas modulationsdotierter GaAs/AlGaAs-Heterostrukturen und wurden über Elektronenstrahl-Lithographie sowie nasschemische Ätztechniken realisiert. Somit entstanden niederdimensionale Leiter mit Kanalbreiten von wenigen 10 nm, deren Leitwert über planare seitliche Gates elektrisch kontrolliert werden kann. Bei den Transportuntersuchungen, die zum Teil im stark nichtlinearen Transportbereich und bei Temperaturen bis hin zu 300 K durchgeführt wurden, stellte sich das Konzept verzweigter Kanalstrukturen als vielversprechend hinsichtlich der Anwendung für eine neuartige Nanoelektronik heraus. So kann eine im Folgenden als Y-Transistor bezeichnete, verzweigte Kanalstruktur in Abhängigkeit der äußeren Beschaltung als Differenzverstärker, invertierender Verstärker, bistabiles Schaltelement oder aber auch als logisches Gatter eingesetzt werden. Zudem eröffnet der Y-Transistor einen experimentellen Zugang zu den nichtklassischen Eigenschaften nanometrischer Kapazitäten, die sich von denen rein geometrisch definierter Kapazitäten aufgrund der endlichen Zustandsdichte erheblich unterscheiden können. Für ballistische Y-Verzweigungen tritt zudem ein neuartiger Gleichrichtungseffekt auf, der in Kombination mit den verstärkenden Eigenschaften von Y-Transistoren dazu genutzt wurde, kompakte logische Gatter sowie einen ballistischen Halb-Addierer zu realisieren. / This thesis reports investigations of monolithic semiconductor nanostructures with novel nanoelectronic transport effects. In particular, it is shown that the ballistic motion of electrons in nanoelectronic devices in combination with capacitive coupling of nearby device sections can be used to realize ballistic amplifiers and logic gates. The nanostructures under investigation are based on the two dimensional electron gas of modulation doped GaAs/AlGaAs-heterostructures and were patterned by electron-beam-lithography and wet chemical etching. In this way, low dimensional conductors with widths on the order of a few 10 nm to about 100 nm controlled by in-plane gates were realized. Investigations at temperatures up to 300 K in the nonlinear transport regime show that branched nanojunctions are promising candidates for future nanoelectronic building blocks. Depending on the external circuit, gated Y-branched nanojunctions, here referred to as "Y-transistors", can be used as differential amplifiers, inverting amplifiers, bistable switches and logic gates. In addition, Y-transistors allow the experimental investigation of nonclassical properties of nanoscaled capacitors, which differ significantly from those of macroscopic capacitors due to the different densities of states. Moreover, a novel ballistic rectification effect observed for Y-branched nanojunctions is exploited to realize a ballistic in-plane half-adder with output signals amplified by feedback coupled Y-transistors.

Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário FEI, São Bernardo do Campo, 2018

acase@tulane.edu / Ever since the successful isolation of graphene, plenty of researches have been pursued to study fundamental physics in low-dimensional van der Waals materials, referred to as materials with the existence of out of plane vdW force. Not only graphene but also many other novel vdW materials start to emerge and play important roles in quantum physics. Due to the highly preserved crystal quality of the nanostructures achieved by micromechanical exfoliation, a variety of new phenomenon have been discovered in these novel materials. This dissertation focuses on the discovery and electronic properties study of new vdW materials both in 2D and 1D systems. Semiconducting transition metal dichalcogenides with layered structure have been viewed as the promising channel materials for field-effect transistors (FETs) in modern electronics. To characterize the performance, we have fabricated FETs based on multilayer WS2 thin crystals. By using gold as the contact metal and varying the thickness of the crystal, high-performance FETs with on/off ratio of 108 and mobility up to 234 cm2V-1s-1 at room temperature have been realized. The high performance is associated with the minimized Schottky barrier and a shallow impurity level below the conduction band. Elementary substance and binary compound crystals have limited members belong to 2D or 1D family. Thus, expanding the research to ternary compound materials is necessary. In this regard, we focused on a novel ternary compound 2D material Nb3SiTe6 and studied its magneto-transport. We have discovered that by using such a high crystalline 2D metal, we could study the inelastic electron-phonon (e-ph) interactions involved with reducing dimensions. From 3D bulk to 2D films with a rigid substrate, the weak antilocalization (WAL) signature is gradually enhanced according to our magnetoresistance (MR) measurements. Systematic studies of the temperature dependence of the dephasing rate in the crystal with various thicknesses suggest the suppression of electron-phonon interaction due to quantum confinement of the phonon spectrum. Our work shows great consistency with the long-standing predicted theory. We have successfully expanded the mechanical exfoliation method to 1D material group. As demonstrated by semiconducting quasi-1D materials, Ta2Pd3Se8 (TPdS) and Ta2Pt3Se8 (TPtS), the external force can efficiently break the weak vdW interactions between ribbons. In our work, we have produced ultrathin 1D TPdS and TPtS nanowires, and fabricated 1D FETs showing p-type and n-type transistor behavior respectively. Moreover, we have successfully built the functional logic NOT gate using these two different 1D FETs. / 1 / Xue Liu

Point-of-care (POC) diagnostics presents a giant market opportunity with profound societal impact. In particular, specific detection of DNA and protein markers can be essential for early diagnosis of e.g. cancer, cardiovascular disease, infections or allergies. Today, identification of these markers often requires extensive laboratory work and hence is expensive and time consuming. Current methods for recognition and detection of specific biomolecules are mostly optics based and thus impose severe limitations as to convenience, specificity, sensitivity, parallel processing and cost reduction. Electronic sensors based on silicon nanowire field-effect transistors have been reported to be able to detect biomolecules with concentrations down to femtomolar (fM) level with high specificity. Although the reported capability needs further confirmation, the CMOS-compatible fabrication process of such sensors allows for low cost production and high density integration, which are favorable for POC applications. This thesis mainly focuses on the development of a multiplex detection platform based on silicon nanowire field-effect sensors integrated with a microfluidic system for liquid sample delivery. Extensive work was dedicated to developing a top-down fabrication process of the sensors as well as an effective passivation scheme. The operation mechanism and coupling efficiencies of different gate configurations were studied experimentally with the assistance of numerical simulation and equivalent circuits. Using pH sensing as a model system, large effort was devoted to identifying sources for false responses resulting from the instability of the inert-metal gate electrode. In addition, the drift mechanism of the sensor operating in electrolyte was addressed and a calibration model was proposed. Furthermore, protein detection experiments were performed using small-sized Affibody molecules as receptors on the gate insulator to tackle the Debye screening issue. Preliminary results showed that the directionality of the current changes in the sensors was in good agreement with the charge polarities of the proteins. Finally, a graphene-based capacitor was examined as an alternative to the nanowire device for field-effect ion sensing. Our initial attempts showed some attractive features of the capacitor sensor.

Conventional logic circuit designs are based on fully complementary CMOS logic circuits. In the past decade, many Pass-Transistor Logic (PTL) circuits have been proposed that are claimed to have better performance in area, speed and power. Most current PTL logic circuits are composed of a limited number of basic PTL cells (say 2 to 5 types of cells only). However, current placement-and-routing (P&R) CAD tools are mainly designed based on CMOS cell library which usually contains many cells with different logic functions. Thus the P&R tool does not fully exploit the features of the synthesized PTL gate-level netlists. In this thesis, we present a P&R tool dedicated to the generation of the final physical layout for the PTL netlists that are generated from a PTL synthesizer. This backend tool considers the efficient placement and routing of the PTL cells in order to reduce the area cost and to reduce the impact of the interconnection wirings on speed and power performances. Besides, in this thesis, the critical paths of the PTL netlists will be identified and the corresponding input patterns to activate these critical paths will be generated for post-layout speed simulation using HSPICE or Nanosim. In summary, the layout generator in this thesis performs the P&R of PTL netlists and also automatically find the critical paths and their corresponding input patterns.

Based on the convenience of the use, the traditional display will be replace by the flexible display. According to this reason, it is very important to study on the reliability of the amorphous silicon (a-Si:H) thin-film transistor (TFT) used in LCD under different mechanical strain. In this research, besides of the above-mentioned we also applied AC stress, to understand the influence of AC stress on an a-Si:H TFT under different mechanical strain. The influence of mechanical strain on the performance of an hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) with different channel length and width on metal foil substrate under uniaxial compressive or tensile strain was studied, where the strain is parallel to the TFT source-drain current path. The process of TFT with the maximum temperature 190¢XC exhibited a field-effect mobility of 0.1 cm2/Vs and a threshold voltage of 1.95 V and the leakage current of less than 10-13 A. The TFTs were strained by inward (compression) or outward (tension) cylindrical bending. The mobility had a slightly change under the mechanical strain, which was due to the change in the disorder under bending strain. We also researched on the influence of uniaxial compressive (tensile) strain on the performance of a-Si:H TFTs under different AC stress conditions. When the a-Si:H TFTs were strained and applied AC stress, we found the performance of a-Si:H TFTs were affected more then the flat ones.

In recently yesrs,Thin-film transistors (TFTs) including an active layer of amorphous silicon or polycrystalline silicon have been widely employed as the pixel-driving elements of a liquid crystal display (LCD). Particularly, a-Si:H TFT is advantageous to the production of large screen displays and facilitates mass-production. a-Si:H has high photoconductivity which results in high off-state leakage currents of a-Si:H TFT under light illumination . Particularly, the off-state leakage current under light illumination is a serious problem in the projection and/or video displays which require high intensity backlight illumination.As the resolutions is higher , the TFT¡¦s performance must be higher to achieve the short charge time each line can charge. The performance includes mobility ,on current, off current, photo leakage current, threshold voltage ,and subthrehold swing. Furthermore, the to improve the mobility of thin-film transistors (TFT) to enable total integration of peripheral electronics in flat panel displays and imagers has led to recrystallized polycrystalline silicon (poly-Si) as the material of choice. However, laser recrystallized polycrystalline silicon suffers from high cost , complex processing, and significant nonuniformity over a large area. Indeed, the direct deposition of good-quality low-temperature poly films is highly desirable and constitutes a promising alternative. In this thesis, we use HDPCVD to fabricate direct deposition poly-TFT successfully.Through plasma passivation, we improve the characteristic of device. The photo-Leakage current have been reduced obviously to our device under light illumination, and is benefit to higher intensity light of large screen display. And our TFT device exhibits stable characteristics with voltage and current stress , and it¡¦s also confirmed that the device is reliable. On the characteristic of device, the direct-deposited poly TFT device exhibits higher effective carrier mobility than that of conventional one. For that reason, the high performance provides the potential of the direct-deposited poly TFT to apply for AMLCD and AMOLED technology.

The hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used as switching device for large-area electronics such as active matrix liquid crystal displays (AM-LCDs). a-Si TFT is particularly advantageous to the production of large screen displays and facilitates mass production. When employing an a-Si:H layer, the main objectives are to enhance the field effect mobility and to reduce the off-state current under light illumination. The increase of field effect mobility results in wide application of a-Si:H TFTs in high resolution LCDs. On the other hand, a-Si:H has high photoconductivity which results in high off-state current of a-Si:H TFT under light illumination. The off-state leakage current under light illumination is, in particular, a serious problem in the projection and/or multimedia displays that require high intensity backlight illumination. Minimizing the off-current increase by a-Si photosensitivity is an important design consideration for achieving highimage-quality LCDs. TFT off-current increase by photoillumination of a-Si decreases the charge stored on the pixel during the TFT off-time, and results in gray-scale shading, flicker, crosstalk and other display nonuniformity in the LCD. The fluorine incorporated amorphous silicon [a-Si:H(:F)] and amorphous silicon (a-Si:H) were illuminated with backlight to investigate electrical characteristics. The effect of different [SiF4] / [ SiH4] ratio on the performance of a-Si:H(:F) TFTs was also studied. We found the density of states in the gap of a-Si:H(:F) will be modified by the introduction of F into a-Si:H and resulting the shift of the Fermi level toward the valence band edge. The density-of-states increasing cause more recombination centers for electrons and holes to increase the carrier recombination rate. The shift in the Fermi level leads to a reduction of the photoconductivity of a-Si:H(:F). Due to these two important factor, the photo leakage current decreases.

The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this thesis, we fabricate another new structure (asymmetry dual-gate TFTs).For asymmetry dual-gate TFTs, the ITO back gate is extended to the middle of the channel and only covered on the drain contact. The new structure has the advantages of dual-gate TFTs. With dual-channel conduction, it exhibit higher Ion and lower photo leakage current performance than the conventional inverted staggered TFTs. In addition, we use the asymmetry dual-gate structure to investigate how the parasitic capacitance influences the feed-through voltage by C-V measurement. We also to investigate the influences of electrical characteristics with the ITO back gate whether or not overlap the source contact. The asymmetry in on current with source-drain swapping can be attributed to the difference in the ITO back gate whether overlaps the source contact. Finally, it simulated the process of the degradation on the TFTs to find the stability mechanism of the TFTs.

In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing.