The paper discusses the theoretical analysis and the experimental work done to describe the cause of intermodulation distortion in class C transistorized amplifiers. A mathematical basis for the intermodulation was derived using a single frequency input and a second frequency introduced into the output of the amplifier. It was followed by experimental work performed to justify the theory. These experiments used both pulsed and sinusoidal drives as amplifier inputs. Also, a feedback method along with the transistor's operating point was shown to reduce the intermodulation distortion produced by the amplifier. Finally, a short discussion on the results and some of the applications of this research to V.H.F. amplifiers was presented.

The main objective of this work is to develop and optimize a process for the fabrication of basic semiconductor devices in silicon using the Modu-lab toolset in the MicrON 636 Whittemore cleanroom facility. This toolset is designed to work with four-inch silicon wafers, in a class 10000 cleanroom. Early work on this process produced functioning devices, with low yield and little to no process control. Three aspects of the process were therefore selected for optimization in this work. The oxidation of the surface of the silicon wafers could not be made to follow models proposed by and accepted in the literature. By carefully changing the airflow in the oxidation furnace module, the uniformity of the oxide layer and the agreement of the growth with models increases to acceptable levels. Also, the effects of redistribution of dopant species due to growth of the oxide layer and the subsequent thermal processing are examined qualitatively. Phosphorus diffusion in single-crystal silicon has a complex diffusion mechanism involving charged-vacancies, with concentration-dependent diffusion coefficients. It is therefore a complex mathematical problem to model the diffusion of phosphorus from a solid source within the crystal. An empirical model is proposed that accurately predicts the junction depth and sheet resistance of diffused phosphorus layers within the silicon wafer. Throughout the course of the process it is necessary to monitor the characteristics of the wafers to assure proper conditions. A semiconductor parameter analyzer has been created for this purpose. Our system uses a Keithley model 2400 source meter, Signatone probe station and four-point probe stage, and a PC to measure DC I-V electrical characteristics of materials and devices. The measurements of sheet resistance, as well as device characterization of resistors, p-n junction diodes, and nMOSFETs provides feedback about the accuracy of processing steps, as well as a pedagogical tool for illustrating semiconductor device physics and operation. / Master of Science

Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.

La réduction (« scaling ») continue des dimensions des transistors MOSFET nous a conduits à l'ère de la nanoélectronique. Le transistor à effet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture «nanofil canal» est considéré comme un candidat possible pour le scaling des MOSFET jusqu'à la fin de la roadmap. Parallèlement au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propositions de nouveaux dispositifs, exploitant des phénomènes nanométriques, ont été faites. Ainsi, le transistor monoélectronique (SET), utilisant le phénomène de «blocage de Coulomb», et le transistor à atome unique (SAT), en tant que transistors de dimensions ultimes, sont les premiers dispositifs nanoélectroniques visant de nouvelles applications comme la logique à valeurs multiples ou l'informatique quantique. Bien que le SET a été initialement proposé comme un substitut au CMOS («Au-delà du dispositif CMOS»), il est maintenant largement considéré comme un complément à la technologie CMOS permettant de nouveaux circuits fonctionnels. Toutefois, la faible température de fonctionnement et la fabrication incompatible avec le procédé CMOS ont été des contraintes majeures pour l'intégration SET avec la technologie FET industrielle. Cette thèse répond à ce problème en combinant les technologies CMOS de dimensions réduites, SET et SAT par le biais d'un schéma d'intégration unique afin de fabriquer des transistors « Trigate » nanofil. Dans ce travail, pour la première fois, un SET fonctionnant à température ambiante et fabriqués à partir de technologies CMOS SOI à l'état de l'art (incluant high-k/grille métallique) est démontré. Le fonctionnement à température ambiante du SET nécessite une île (ou canal) de dimensions inférieures à 5 nm. Ce résultat est obtenu grâce à la réduction du canal nanofil ‘‘trigate'' à environ 5 nm de largeur. Une étude plus approfondie des mécanismes de transport mis en jeu dans le dispositif est réalisée au moyen de mesures cryogéniques de conductance. Des simulations NEGF tridimensionnelles sont également utilisées pour optimiser la conception du SET. De plus, la cointégration sur la même puce de MOSFET FDSOI et SET est réalisée. Des circuits hybrides SET-FET fonctionnant à température ambiante et permettant l'amplification du courant SET jusque dans la gamme des milliampères (appelé «dispositif SETMOS» dans la littérature) sont démontrés de même que de la résistance différentielle négative (NDR) et de la logique à valeurs multiples. Parallèlement, sur la même technologie, un transistor à atome unique fonctionnant à température cryogénique est également démontré. Ceci est obtenu par la réduction de la longueur de canal MOSFET à environ 10 nm, si bien qu'il ne comporte plus qu'un seul atome de dopant dans le canal (diffusée à partir de la source ou de drain). A basse température, le transport d'électrons à travers l'état d'énergie de ce dopant unique est étudié. Ces dispositifs fonctionnent également comme MOSFET à température ambiante. Par conséquent, une nouvelle méthode d'analyse est développée en corrélation avec des caractéristiques à 300K et des mesures cryogéniques pour comprendre l'impact du dopant unique sur l'échelle MOSFET à température ambiante. / Continuous scaling of MOSFET dimensions has led us to the era of nanoelectronics. Multigate FET (MuGFET) architecture with ‘nanowire channel' is being considered as one feasible enabler of MOSFET scaling to end-of-roadmap. Alongside classical CMOS or Moore's law scaling, many novel device proposals exploiting nanoscale phenomena have been made either. Single Electron Transistor (SET), with its unique ‘Coulomb Blockade' phenomena, and Single Atom Transistor (SAT), as an ultimately scaled transistor, are prime nanoelectronic devices for novel applications like multivalued logic, quantum computing etc. Though SET was initially proposed as a substitute for CMOS (‘Beyond CMOS device'), it is now widely considered as a compliment to CMOS technology to enable novel functional circuits. However, the low operation temperature and non-CMOS fabrication process have been major limitations for SET integration with FET. This thesis makes an effort at combining scaled CMOS, SET and SAT through a single integration scheme enabling trigate nanowire-FET, SET or SAT. In this work, for the first time, fabrication of room temperature operating SET on state-of-the-art SOI CMOS technology (featuring high-k/metal gate) is demonstrated. Room temperature operation of SET requires an island (or channel) with dimensions of 5 nm or less. This is achieved through reduction of trigated nanowire channel to around 5 nm in width. Further study of carrier transport mechanisms in the device is carried out through cryogenic conductance measurements. Three dimensional NEGF simulations are also employed to optimize SET design. As a step further, cointegration of FDSOI MOSFET and SET on the same die is carried out. Room temperature hybrid SET-FET circuits enabling amplification of SET current to micro-ampere range (proposed as ‘SETMOS device' in literature), negative differential resistance (NDR) and multivalued logic are shown. Alongside this, on the same technology, a Single Atom Transistor working at cryogenic temperature is also demonstrated. This is achieved through scaling of MOSFET channel length to around 10 nm that enables having a single dopant atom in channel (diffused from source or drain). At low temperature, electron transport through the energy state of this single dopant is studied. These devices also work as scaled MOSFETs at room temperature. Therefore, a novel analysis method is developed correlating 300 K characteristics with cryogenic measurements to understand the impact of single dopant on scaled MOSFET at room temperature.

Diese Arbeit stellt eine eingehende Studie des sogenannten Vertikalen Organischen Feld-Effekt-Transistors (VOFET) dar, einer neuen Transistor-Geometrie, welche dem stetig wachsenden Bereich der organischen Elektronik entspringt. Dieses neuartige Bauteil hat bereits bewiesen, dass es in der Lage ist, eine der fundamentalen Einschränkungen herkömmlicher organischer Feld-Effekt-Transistoren (OFETs) zu überwinden: Die für Schaltfrequenz und An-Strom wichtige Kanallänge des Transistors kann im VOFET stark reduziert werden, ohne dass teure und komplexe Strukturierungsmethoden genutzt werden müssen. Das genaue Funktionsprinzip des VOFET ist bisher jedoch weitgehend unerforscht. Durch den Vergleich von experimentellen Daten mit Simulationsdaten des erwarteten Bauteil-Verhaltens wird hier ein erstes, grundlegendes Verständnis des VOFETs erarbeitet. Die so gewonnenen Erkenntnisse werden im Folgenden genutzt, um bestimmte Parameter des VOFETs kontrolliert zu manipulieren. So wird beispielsweise gezeigt, dass die Morphologie des organischen Halbleiters, und damit seine Abscheidungsparameter, sowohl für die VOFET-Herstellung als auch für den Ladungsträgertransport im fertigen Bauteil eine wichtige Rolle spielen. Weiterhin wird gezeigt, dass der VOFET, genau wie der konventionelle OFET, durch das Einbringen von Kontaktdotierung deutlich verbessert werden kann. Mit Hilfe dieser Ergebnisse kann gezeigt werden, dass das Funktionsprinzip des VOFETs mit dem eines konventionellen OFETs nahezu identisch ist, wenn man von geringen Abweichungen aufgrund der unterschiedlichen Geometrien absieht. Basierend auf dieser Erkenntnis wird schließlich ein VOFET präsentiert, welcher im Inversionsmodus betrieben werden kann und so die Lücke zur konventionellen MOSFET-Technologie schließt. Dieser Inversions-VOFET stellt folglich einen vielversprechenden Ansatz für leistungsfähige organische Transistoren dar, welche als Grundbausteine für komplexe Elektronikanwendungen auf flexiblen Substraten genutzt werden können. / This work represents a comprehensive study of the so-called vertical organic field-effect transistor (VOFET), a novel transistor geometry originating from the fast-growing field of organic electronics. This device has already demonstrated its potential to overcome one of the fundamental limitations met in conventional organic transistor architectures (OFETs): In the VOFET, it is possible to reduce the channel length and thus increase On-state current and switching frequency without using expensive and complex structuring methods. Yet the VOFET's operational principles are presently not understood in full detail. By simulating the expected device behaviour and correlating it with experimental findings, a basic understanding of the charge transport in VOFETs is established and this knowledge is subsequently applied in order to manipulate certain parameters and materials in the VOFET. In particular, it is found that the morphology, and thus the deposition parameters, of the organic semiconductor play an important role, both for a successful VOFET fabrication and for the charge transport in the finished device. Furthermore, it is shown that VOFETs, just like their conventional counterparts, are greatly improved by the application of contact doping. This result, in turn, is used to demonstrate that the VOFET essentially works in almost exactly the same way as a conventional OFET, with only minor changes due to the altered contact arrangement. Working from this realisation, a vertical organic transistor is developed which operates in the inversion regime, thus closing the gap to conventional MOSFET technology and providing a truly promising candidate for high-performance organic transistors as the building blocks for advanced, flexible electronics applications.

No description available.

As electronics reach nanometer size scales, new avenues of integrating biology and electronics become available. For example, nanoscale field-effect transistors have been integrated with single neurons to detect neural activity. Researchers have also used nanoscale materials to build electronic ears and noses. Another exciting development is the use of nanoscale biosensors for the point-of-care detection of disease biomarkers. This thesis addresses many issues that are relevant for electrical sensing applications in biological environments. As an experimental platform we have used carbon nanotube field-effect transistors for the detection of biological proteins. Using this experimental platform we have probed many of properties that control sensor function, such as surface potentials, the response of field effect transistors to absorbed material, and the mass transport of proteins. Field effect transistor biosensors are a topic of active research, and were first demonstrated in 1962. Despite decades of research, the mass transport of proteins onto a sensor surface has not been quantified experimentally, and theoretical modeling has not been reconciled with some notable experiments. Protein transport is an important issue because signals from low analyte concentrations can take hours to develop. Guided by mass transport modeling we modified our sensors to demonstrate a 2.5 fold improvement in sensor response time. It is easy to imagine a 25 fold improvement in sensor response time using more advanced existing fabrication techniques. This improvement would allow for the detection of low concentrations of analyte on the order of minutes instead of hours, and will open the door point-of-care biosensors. / Graduation date: 2011

No description available.

No description available.

La lumière comprimée est un état du champ électromagnétique pour lequel le bruit, mesuré selon une certaine quadrature est inférieur au bruit du vide. Dans cet ouvrage, nous étudions la possibilité de générer de la lumière micro-onde à partir d’un transistor à effet de champ commercial. D’une part, nous observons le bruit de grenaille du canal drain-source à basse fréquence, ce qui suggère que le canal est cohérent. Ensuite, nous exploitons cette cohérence et procédons à une expérience standard de compression par le bruit de grenaille. D’autre part, nous prédisons, à l’aide d’un modèle simple, la possibilité de comprimer le bruit par modulation de la résistance du canal drain-source pour des mesures de bruit à hautes fréquences. Nous concluons en proposant une mise en œuvre de cette méthode.