International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The performance and cost effectiveness of em bedded processing has greatly enhanced the personal computer's (PC) capability, particularly when used for real-time satellite data acquisition, telemetry processing, command and control operations. Utilizing a transputer based parallel architecture, a modular, reusable, and scalable control system is attainable. The synergism between the personal computer and embedded processing results in efficient, low cost desktop workstations up to 1000 MIPS of performance.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The trend of current data acquisition and recording systems is to capture multiple streams of Pulse Code Modulation (PCM) data on a single media. The MARS II data recording system manufactured by Datatape, the Asynchronous Realtime Multiplexer and Output Reconstructor (ARMOR) systems manufactured by Calculex, Inc., and other systems on the market today are examples of this technology. The quantity of data recorded by these systems can be impressive, and can cause difficulties in post-test data processing in terms of data storage and turn around time to the analyst. This paper describes the system currently in use at the Strategic Systems Combined Test Force B-1B division to simultaneously post-flight process up to twelve independent PCM streams at twice real-time speeds. This system is entirely personal computer (PC) based running the Window NT 4.0 operating system with an internal ISA bus PCM decommutation card. Each PC is capable of receiving and processing one stream at a time. Therefore, the core of the system is twelve PCs each with decommutation capability. All PCs are connected via a fast ethernet network hub. The data processed by this system is IRIG 106 Chapter 8 converted MIL-STD-1553B bus data and Chapter 4 Class I and II PCM data. All system operator inputs are via Distributed Component Object Modeling (DCOM) provided by Microsoft Developers Studio, Versions 5.0 and 6.0, which allows control and status of multiple data processing PCs from one workstation. All data processing software is written in-house using Visual C++ and Visual Basic.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper describes the Real-Time/Post-Flight Processing System (RT/PFP) developed under the Air Force Flight Test Center (AFFTC) Advanced Data Acquisition and Processing Systems (ADAPS) development program. The RT/PFP is currently being deployed at all Range Division Mission Control Facilities as the principal Range Division telemetry processing system. This paper provides an overview of the RT/PFP system, its current capabilities, and future enhancements being developed. The RT/PFP is currently used to support the F-22 flight test program, and to provide telemetry processing support for the AFFTC Range Safety Office. The RT/PFP is also used in a mobile configuration to support the Advanced Fighter Technology Integration program.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / This paper discusses the evolution of the ground satellite communication systems and the efforts made by the Goddard Space Flight Center's (GSFC) Advanced Architectures and Automation (AAA) branch, Code 588 to bring satellite scientific data to the user’s desktop. Primarily, it describes the next generation desktop system, its architecture and processing capabilities, which provide autonomous high-performance telemetry acquisition at the lowest possible cost. It also discusses the planning processes and the applicability of new technologies for communication needs in the next century. The paper is presented in terms simple for those not very familiar with current space programs to understand.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper presents the Mission Integrated Decommutation and Analysis System (MIDAS), a multi-threaded, multi-processing application developed in Microsoft Visual C++ for Windows NT by the Air Force Development Test Center (AFDTC) Eglin AFB, Florida. The primary function of MIDAS is to support post-test processing of instrumentation data by decommutating, logging, and reporting MIL-STD-1553B or pulse code modulated (PCM) encoded data extracted from MARS-II digital tape recordings. MIDAS processes multiple data streams from a single recording, and can process multiple recordings in parallel. MIDAS also serves as a diagnostics tool for investigating data processing anomalies reported during normal production runs. MIDAS is part of an integrated suite of applications developed to provide AFDTC development test and operational test customers with quickly delivered, high-quality data products. Software development is underway to support the processing of Digital Data Acquisition and On-Board Recording Standard (DDAS) packetized telemetry data. DDAS is derived from the Consultative Committee for Space Data Systems (CCSDS) standard. [MARS-II is the digital acquisition and recording system supported by MIDAS. MARS-II was developed by DATATAPE, Incorporated, Pasadena, California. It records up to 20 gigabytes of mission data across as many as eight channels of MIL-STD-1553B or PCM encoded data. Digital recording technology provides an alternative to traditional analogbased telemetry ground systems.]

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.