Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-05-21T13:19:36Z No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-01T12:13:22Z (GMT) No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Made available in DSpace on 2018-06-01T12:33:57Z (GMT). No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) Previous issue date: 2018-03-28 / ? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia natural de um circuito implementado com Blade, onde o monitoramento cont?nuo para detec??o de viola??es de atraso fornece a informa??o necess?ria para a detec??o concorrente de viola??es que extrapolam a capacidade de recupera??o do circuito resiliente. A integra??o de todas as contribui??es fornece uma cobertura de falha satisfat?ria para um custo de ?rea que, para os circuitos avaliados nesta Tese, pode variar de 4,24% a 6,87%, enquanto que a abordagem Scan para os mesmos circuitos apresenta custo que varia de 50,19% a 112,70% em ?rea, respectivamente. As contribui??es desta Tese demonstraram que, com algumas melhorias na arquitetura do Blade, ? poss?vel expandir sua confiabilidade para al?m de um sistema de toler?ncia a viola??es de atraso no caminho de dados, e tamb?m um avan?o para teste de falhas (inclusive falhas online) de todo o circuito, bem como melhorar seu rendimento, e lidar com quest?es de envelhecimento. / As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade?s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.

A circuit testing nowadays is expensive and complex process. That’s why circuits testing, errors finding and fixing require more and more investments. One of possible ways of reducing cost and speed up testing process is increasing controllability and observability of circuits. It takes a lot of time to find out circuit’s controllability and observability that’s why that process have to be computerized. For that purpose was decided to create software which will be helpful for circuit designers in that process. As a result it will help designers in making design for testability schemes. Research and training action for system on chip using internet software is dedicated for users that have C/C++ system on chip code from every place in the world, using only web browser, would be able put that code in to the server, test it and retrieve it‘s observability results in text and visual modes and also increase system’s on chip observability level. And as well review and get acquainted with systems on chip that are already on the server and are stored on it. Software architecture uses client-server mode. All computations are performed on a server side. System is realized on Apache server with Linux OS. System modules are realized using HTML, JAVA, PHP, JavaScript, C++ and CGI programming languages. Web page is working independent from users OS, user needs only web browser (Internet Explorer not older than 3.0 ver., Opera not older than 6.0 ver., Netscape Navigator not older... [to full text]

Ο όγκος των δεδομένων που απαιτούνται για τον έλεγχο της ορθής λειτουργίας ενός συστήματος που υλοποιείται σε ένα ολοκληρωμένο κύκλωμα είναι πάρα πολύ μεγάλος. Αυτό συνεπάγεται ότι ο χρόνος που απαιτείται για τον έλεγχο της ορθής λειτουργίας του ολοκληρωμένου κυκλώματος μπορεί να είναι απαγορευτικά μεγάλος. Για τη μείωση του απαιτούμενου χρόνου χρησιμοποιούνται διάφορες τεχνικές συμπίεσης των δεδομένων δοκιμής. Κάποιες από αυτές τις τεχνικές βασίζονται στην αποστολή κοινών δεδομένων δοκιμής ταυτόχρονα σε περισσότερες από μία μονάδες του ολοκληρωμένου κυκλώματος. Στην εργασία αυτή υλοποιούμε μια από αυτές τις τεχνικές που βασίζεται στην ύπαρξη μονοπατιών ολίσθησης (scan paths) στις μονάδες του ολοκληρωμένου κυκλώματος. Για την περαιτέρω μείωση του χρόνου που απαιτείται για τον έλεγχο της ορθής λειτουργίας του ολοκληρωμένου κυκλώματος γίνεται χρονοπρογραμματισμός της σειράς με την οποία θα ελεγχθεί η ορθή λειτουργία των διαφόρων μονάδων του ολοκληρωμένου κυκλώματος. / The volume of data that is required to test a SoC is too much big. This means that the time that is required for testing can be prohibitorily big. For the reduction of required time are used various techniques of data compaction.Some of these techniques are based on broadcasting the same value to all of the cores on a SoC.In this work we use one of these techniques that are based on the existence of scan chains in the core (broadcast scan).For further reduction of time that is required for testing a circuit we use a core testing schedule algorithm.

This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.

Companies are under constant pressure to adapt and improve their processes to staycompetitive. Since most of their processes are handled by software, it also needs toconstantly change. Those improvements and changes add up over time and increase thecomplexity of the system, which in turn prevents the company from further adaption.In order to change and improve existing business processes and their implementation withinsoftware, several stakeholders have to go through a long process. Current IT methodologies arenot suitable for such a dynamic environment. The analysis of this change process shows thatfour software characteristics are important to speed it up. They are: transparency, adaptability,testability and reparability. Transparency refers to the users capability to understand what thesystem is doing, where and why. Adaptability is a mainly technical characteristic that indicatesthe capability of the system to evolve or change. Testability allows automated testing andvalidation for correctness without requiring manual checks. The last characteristic is reparability,which describes the possibility to bring the system back into a consistent and correct state, evenif erroneous software was deployed.An architecture and software development patterns are evaluated to build an overall programmingmodel that provides the software characteristics. The overall architecture is basedon microservices, which facilitates decoupling and maintainability for the software as well asorganizations. Command Query Responsibility Segregation decouples read from write operationsand makes data changes explicit. With Event Sourcing, the system stores not only the currentstate, but all historic events. It provides a built-in audit trail and is able to reproduce differentscenarios for troubleshooting and testing.A demo process is defined and implemented within multiple prototypes. The design of theprototype is based on the programming model. It is built in Javascript and implements Microservices,CQRS and Event Sourcing. The prototypes show and validate how the programmingmodel provides the software characteristics. Software built with the programming model allowscompanies to iterate faster at scale. Since the programming model is suited for complex processes,the main limitation is that the validation is based on a demo process that is simpler and thebenefits are hard to quantify. / ör att fortsatt vara konkurrenskraftiga är företag under konstant press att anpassa ochförbättra sina processer. Eftersom de flesta processer hanteras av programvara, behöveräven de ständigt förändras. Övertiden leder dessa förbättringar och förändringar till ökadsystemkomplexitet, vilket i sin tur hindrar företaget från ytterligare anpassningar. För attförändra och förbättra befintliga affärsprocesser och dess programvara, måste idag typiskt fleraaktörer vara en del av en lång och tidskrävande process. Nuvarande metoder är inte lämpade fören sådan dynamisk miljö. Detta arbete har fokuserat på fyra programvaruegenskaper som ärviktiga för att underlätta förändringsprocesser. Dessa fyra egenskaper är: öppenhet, anpassningsförmåga,testbarhet och reparerbarhet. Öppenhet, hänvisar till förmågan att förstå varför, var ochvad systemet gör. Anpassningsbarhet är huvudsakligen en teknisk egenskap som fokuserar påsystemets förmåga att utvecklas och förändras. Testbarhet strävar efter automatisk testning ochvalidering av korrekthet som kräver ingen eller lite manuell kontroll. Den sista egenskapen ärreparerbarhet, som beskriver möjligheten att återhämta systemet till ett konsekvent och korrekttillstånd, även om felaktig programvara har använts. En programmeringsmodell som rustarprogramvara med de ovan beskrivna programegenskaperna är utvecklad i detta examensarbete.Programmeringsmodellens arkitektur är baserad på diverse micro-tjänster, vilka ger brafrånkopplings- och underhållsförmåga för en programvara, samt användarorganisationerna.Command Query Responsibility Segregation (CQRS) frånkopplar läsoperationer från skrivoperationeroch gör ändringar i data explicita. Med Event Sourcing lagrar systemet inte endastdet nuvarande tillståndet, utan alla historiska händelser. Modellen förser användarna medett inbyggt revisionsspår och kan reproducera olika scenarion för felsökning och testning. Endemoprocess är definierad och implementerad i tre olika prototyper. Designen av prototypernaär baserad på den föreslagna programmeringsmodellen. Vilken är byggd i Javascript och implementerarmicro-tjänster, CQRS och Event Sourcing. Prototyperna visar och validerar hurprogrammeringsmodellen ger programvaran rätt egenskaper. Programvara byggd med dennaprogrammeringsmodell tillåter företag att iterera snabbare. De huvudsakliga begränsningarna iarbetet är att valideringen är baserad på en enklare demoprocess och att dess fördelar är svåraatt kvantifiera.