The article identifies the challenges during the system and specifically the software development process for safety critical electro-hydraulic control systems by using the example of the hydrostatic driveline with a four speed transmission of a feeder mixer. An optimized development approach for mobile machinery has to fulfill all the requirements according to the Machinery Directive 2006/42/EC, considering functional safety, documentation and testing requirements from the beginning and throughout the entire machine life cycle. The functionality of the drive line control could be verified in advance of the availability of a prototype by using a “software-in-the-loop” development approach, based on a MATLAB/SIMULINK model of the drive line in connection with the embedded software.

Este trabalho apresenta uma plataforma e uma técnica para o melhoramento da eficiência da graduação de falhas stuck-at de padrões de teste através do uso de co-emulação de hardware. Os fabricantes de Circuitos Integrados continuamente buscam novas formas de testar seus dispositivos com o intuito de distribuir peças sem defeitos aos seus clientes. Scan é uma técnica bem conhecida que consegue alta cobertura de falhas com eficiência. As demandas por novos recursos motivam a criação de sistemas complexos que fazem uso de uma mistura de blocos analógicos e digitais com uma interface de comunicação, difícil de ser coberta pelos padrões de scan. Adicionalmente, a lógica que configura o chip para cada um dos diferentes modos de operação, algumas interfaces com circuitos de teste de memória (BIST), divisores ou geradores de clocks assíncronos, entre outros, são exemplos de circuitos que se encontram bloqueados em scan ou possuem poucos pontos de observação/controle. Este trabalho descreve uma plataforma baseada em FPGA que usa modelos heterogêneos para co-emular blocos digitais, analógicos e de memória para a graduação de padrões em sistemas complexos. Adicionalmente introduziu-se quatro tipos de modelos que podem ser usados no FPGA, e os resultados de aplicar a técnica de co-emulação de falhas em alguns circuitos de benchmark incluindo ISCAS89, um conversor análogo digital, portas configuráveis de entrada/saída e um controlador de memória. / A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA based-platform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

Dans cette thèse, nous analysons les vulnérabilités introduites par les infrastructures de test, comme les chaines de scan, utilisées dans les circuits intégrés digitaux dédiés à la cryptographie sur la sécurité d'un système. Nous développons de nouvelles attaques utilisant ces infrastructures et proposons des contre-mesures efficaces. L'insertion des chaînes de scan est la technique la plus utilisée pour assurer la testabilité des circuits numériques car elle permet d'obtenir d'excellents taux de couverture de fautes. Toutefois, pour les circuits intégrés à vocation cryptographique, les chaînes de scan peuvent être utilisées comme une porte dérobée pour accéder à des données secrètes, devenant ainsi une menace pour la sécurité de ces données. Nous commençons par décrire une série de nouvelles attaques qui exploitent les fuites d'informations sur des structures avancées de conception en vue du test telles que le compacteur de réponses, le masquage de valeur inconnues ou le scan partiel, par exemple. Au travers des attaques que nous proposons, nous montrons que ces structures ne protégent en rien les circuits à l'inverse de ce que certains travaux antérieurs ont prétendu. En ce qui concerne les contre-mesures, nous proposons trois nouvelles solutions. La première consiste à déplacer la comparaison entre réponses aux stimuli de test et réponses attenduesde l'équipement de test automatique vers le circuit lui-même. Cette solution entraine un surcoût de silicium négligeable, n'aucun impact sur la couverture de fautes. La deuxième contre-mesure viseà protéger le circuit contre tout accès non autorisé, par exemple au mode test du circuit, et d'assurer l'authentification du circuit. A cet effet, l'authentification mutuelle utilisant le protocole de Schnorr basé sur les courbes elliptiques est mis en oeuvre. Enfin, nous montronsque les contre-mesures algorithmiques agissant contre l'analyse différentielle peuvent être également utilisées pour se prémunir contre les attaques par chaine de scan. Parmi celles-ci on citera en particulier le masquage de point et le masquage de scalaire. / In this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks.

Este trabalho apresenta uma plataforma e uma técnica para o melhoramento da eficiência da graduação de falhas stuck-at de padrões de teste através do uso de co-emulação de hardware. Os fabricantes de Circuitos Integrados continuamente buscam novas formas de testar seus dispositivos com o intuito de distribuir peças sem defeitos aos seus clientes. Scan é uma técnica bem conhecida que consegue alta cobertura de falhas com eficiência. As demandas por novos recursos motivam a criação de sistemas complexos que fazem uso de uma mistura de blocos analógicos e digitais com uma interface de comunicação, difícil de ser coberta pelos padrões de scan. Adicionalmente, a lógica que configura o chip para cada um dos diferentes modos de operação, algumas interfaces com circuitos de teste de memória (BIST), divisores ou geradores de clocks assíncronos, entre outros, são exemplos de circuitos que se encontram bloqueados em scan ou possuem poucos pontos de observação/controle. Este trabalho descreve uma plataforma baseada em FPGA que usa modelos heterogêneos para co-emular blocos digitais, analógicos e de memória para a graduação de padrões em sistemas complexos. Adicionalmente introduziu-se quatro tipos de modelos que podem ser usados no FPGA, e os resultados de aplicar a técnica de co-emulação de falhas em alguns circuitos de benchmark incluindo ISCAS89, um conversor análogo digital, portas configuráveis de entrada/saída e um controlador de memória. / A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA based-platform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

<p>Integrated circuits (ICs) are becoming increasingly complex, which leadsto long design and development times. Designing ICs in a modular fashionis efficient to shorten design and development times. Due to imperfection inIC manufacturing, all ICs are tested. An IC designed in a modular fashioncan be tested in a modular manner. To enable modular test, the IEEE 1500std has been developed to enable isolation and access of modules. Whilethe IEEE 1500 std is adopted, there is yet no commercial tool available.</p><p>In this thesis we have (1) developed an IEEE 1500 std wrapper and (2)included it in a design flow based on a commercial tool, and developed scriptto automate the process. Given a module in VHDL, our design automationautomatically makes synthesis, scan insertion, test generation (ATPG), andwrapper insertion. We have applied the design flow to several benchmarksand through simulation verified the correctness.</p>

I evaluate the methods of cladistic parsimony and maximum likelihood in phylogenetic systematics by their affinity to Popper‘s degree of corroboration. My work analyzes an important recent exchange between the proponents of the two methods. Until this exchange, only advocates of cladistic parsimony have claimed a basis for their method on epistemological grounds through corroboration. Advocates of maximum likelihood, on the other hand, have based the rational justification for their method largely on statistical grounds. In Part One I outline corroboration in terms of content, severity of test and explanatory power. In Part Two I introduce the two methods. In Part Three I analyze three important debates. The first involves the appropriate probability interpretation for phylogenetics. The second is about severity of test. The third concerns explanatory power. In Part Four I conclude that corroboration can decide none of these debates, and therefore cannot decide the debate between cladistic parsimony and maximum likelihood.

I evaluate the methods of cladistic parsimony and maximum likelihood in phylogenetic systematics by their affinity to Popper‘s degree of corroboration. My work analyzes an important recent exchange between the proponents of the two methods. Until this exchange, only advocates of cladistic parsimony have claimed a basis for their method on epistemological grounds through corroboration. Advocates of maximum likelihood, on the other hand, have based the rational justification for their method largely on statistical grounds. In Part One I outline corroboration in terms of content, severity of test and explanatory power. In Part Two I introduce the two methods. In Part Three I analyze three important debates. The first involves the appropriate probability interpretation for phylogenetics. The second is about severity of test. The third concerns explanatory power. In Part Four I conclude that corroboration can decide none of these debates, and therefore cannot decide the debate between cladistic parsimony and maximum likelihood.

A geração de testes para circuitos combinacionais com fan-outs recovergentes é um problema NP-completo. Com o rápido crescimento da complexidade dos circuitos fabricados, a geração de testes passou a ser um sério problema para a indústria de circuitos integrados. Muitos algoritmos de ATPG (Automatic Test Pattern Generation) baseados no algoritmo D, usam heurísticas para guiar o processo de tomada de decisão na propagação n e na justificação das constantes de forma a aumentar sua eficiencia. Existem heurísticas baseadas em medidas funcionais, estruturais e probabilísticas. Estas medidas são normalmente referidas como observabilidade e controlabilidade que fazem parte de um conceito mais geral, a testabilidade. As medidas que o algoritmo utiliza podem ser calculadas apenas uma vez, durante uma etapa de pré-processamento (medidas de testabilidade estáticas - STM's), ou dinamicamente, recalculando estas medidas durante o processamento sempre que elas forem necessárias (medidas de testabilidade dinâmicas — DTM's). Para alguns circuitos, o use de medidas dinâmicas ao invés de medidas estáticas diminui o número de backtrackings pcir vetor gerado. Apesar disto, o tempo total de CPU por vetor aumenta. Assim, as DTM's só devem ser utilizadas quando as STM's não apresentam uma boa performance. Isto pode ser feito utilizando-se as medidas estáticas ate um certo número de backtrackings. Se o padrão de teste não for encontrado, então medidas dinâmicas são utilizadas. Entretanto, a necessário ainda buscar formas de melhorar o processo dinâmico, diminuindo o custo computacional. A proposta original do calculo das DTM's apresenta algumas técnicas, baseadas em selective tracing, com o objetivo de reduzir o custo computacional. Este trabalho analisa o use combinado de heurísticas e propõe técnicas alternativas, na forma das heurísticas de recalculo parcial e recalculo de linhas não free, que visam minimizar o overhead do calculo das DTM's. E proposta ainda a técnica de Pré-implicação que transfere a complexidade do algoritmo para a memória. Isto é feito através de um preprocessamento que armazena informações necessárias para a geração de todos os vetores de teste. De outra forma estas informações teriam de ser calculadas na geração de cada um destes vetores. A implementação do algoritmo D com as várias heurísticas permitiu a realização de um experimento pratico. Isto possibilitou a análise quantitativa da performance do algoritmo D para vários tipos de circuitos e demonstrou a eficiência de uma das heurísticas propostas neste trabalho. / The test generation for combinational circuits that contain reconvergence is a NP-complete problem. With the rapid increase in the complexity of the fabricated circuits, the generation of test patterns poses a serious problem to the IC industry. A number of existing ATPG algorithms based on the D algorithm use heuristics to guide the decision process in the D-propagation and justification to improve the efficiency. The heuristics used by ATPG algorithm are based on structural, functional and probabilistics measures. These measures are commonly referred to as line controllability and observability and they are combined under the , more general notion of testability. The measures used by ATPG algorithms can be computed only once, during a preprocessing stage (static testability measures - STM's) or can be calculated dinamically, updating the testability measures during the test generation process (dymanic testability measures - DTM's). For some circuits, replacing STM's by DTM's decreases the average number of backtrackings per generated vector. Despite these decrease, the total CPU time per generated vector is greater when using DTM's instead of STM's. So, DTM's only must be used if the STM's don't present a good performance. This can be done by STM's until a certain number of backtrackings. If a test pattern has still not been found, then DTM's are used. Therefore, it is yet necessary to search for ways to improve the dynamic process and decrease the CPU time requirements. In the original approach some techniques for reducing the computational overhead of DTM's based on the well-know technique of selective path tracing are presented. In this work, the combined use of heuristics are analised and alternative techniques — the heuristics of partial recalculus and not free lines recalculus — are proposed. These alternative techniques were developed in order to minimize the overhead of the DTM's calculus. It is yet proposed the pre-implication technique which transfers to memory the algorithm complexity. It includes a preprocessing stage which storages all necesary informations to the generation of all test vectors. So, these informations don't need be computed in the generation of each test vector. The implementation of the D-Algorithm with diferent heuristics has possibilited a practical experiment. It was possible to analise the performance of the D-Algorithm on diferent circuit types and to demonstrate the efficiency of one of the proposed heuristics.

A geração de testes para circuitos combinacionais com fan-outs recovergentes é um problema NP-completo. Com o rápido crescimento da complexidade dos circuitos fabricados, a geração de testes passou a ser um sério problema para a indústria de circuitos integrados. Muitos algoritmos de ATPG (Automatic Test Pattern Generation) baseados no algoritmo D, usam heurísticas para guiar o processo de tomada de decisão na propagação n e na justificação das constantes de forma a aumentar sua eficiencia. Existem heurísticas baseadas em medidas funcionais, estruturais e probabilísticas. Estas medidas são normalmente referidas como observabilidade e controlabilidade que fazem parte de um conceito mais geral, a testabilidade. As medidas que o algoritmo utiliza podem ser calculadas apenas uma vez, durante uma etapa de pré-processamento (medidas de testabilidade estáticas - STM's), ou dinamicamente, recalculando estas medidas durante o processamento sempre que elas forem necessárias (medidas de testabilidade dinâmicas — DTM's). Para alguns circuitos, o use de medidas dinâmicas ao invés de medidas estáticas diminui o número de backtrackings pcir vetor gerado. Apesar disto, o tempo total de CPU por vetor aumenta. Assim, as DTM's só devem ser utilizadas quando as STM's não apresentam uma boa performance. Isto pode ser feito utilizando-se as medidas estáticas ate um certo número de backtrackings. Se o padrão de teste não for encontrado, então medidas dinâmicas são utilizadas. Entretanto, a necessário ainda buscar formas de melhorar o processo dinâmico, diminuindo o custo computacional. A proposta original do calculo das DTM's apresenta algumas técnicas, baseadas em selective tracing, com o objetivo de reduzir o custo computacional. Este trabalho analisa o use combinado de heurísticas e propõe técnicas alternativas, na forma das heurísticas de recalculo parcial e recalculo de linhas não free, que visam minimizar o overhead do calculo das DTM's. E proposta ainda a técnica de Pré-implicação que transfere a complexidade do algoritmo para a memória. Isto é feito através de um preprocessamento que armazena informações necessárias para a geração de todos os vetores de teste. De outra forma estas informações teriam de ser calculadas na geração de cada um destes vetores. A implementação do algoritmo D com as várias heurísticas permitiu a realização de um experimento pratico. Isto possibilitou a análise quantitativa da performance do algoritmo D para vários tipos de circuitos e demonstrou a eficiência de uma das heurísticas propostas neste trabalho. / The test generation for combinational circuits that contain reconvergence is a NP-complete problem. With the rapid increase in the complexity of the fabricated circuits, the generation of test patterns poses a serious problem to the IC industry. A number of existing ATPG algorithms based on the D algorithm use heuristics to guide the decision process in the D-propagation and justification to improve the efficiency. The heuristics used by ATPG algorithm are based on structural, functional and probabilistics measures. These measures are commonly referred to as line controllability and observability and they are combined under the , more general notion of testability. The measures used by ATPG algorithms can be computed only once, during a preprocessing stage (static testability measures - STM's) or can be calculated dinamically, updating the testability measures during the test generation process (dymanic testability measures - DTM's). For some circuits, replacing STM's by DTM's decreases the average number of backtrackings per generated vector. Despite these decrease, the total CPU time per generated vector is greater when using DTM's instead of STM's. So, DTM's only must be used if the STM's don't present a good performance. This can be done by STM's until a certain number of backtrackings. If a test pattern has still not been found, then DTM's are used. Therefore, it is yet necessary to search for ways to improve the dynamic process and decrease the CPU time requirements. In the original approach some techniques for reducing the computational overhead of DTM's based on the well-know technique of selective path tracing are presented. In this work, the combined use of heuristics are analised and alternative techniques — the heuristics of partial recalculus and not free lines recalculus — are proposed. These alternative techniques were developed in order to minimize the overhead of the DTM's calculus. It is yet proposed the pre-implication technique which transfers to memory the algorithm complexity. It includes a preprocessing stage which storages all necesary informations to the generation of all test vectors. So, these informations don't need be computed in the generation of each test vector. The implementation of the D-Algorithm with diferent heuristics has possibilited a practical experiment. It was possible to analise the performance of the D-Algorithm on diferent circuit types and to demonstrate the efficiency of one of the proposed heuristics.

A geração de testes para circuitos combinacionais com fan-outs recovergentes é um problema NP-completo. Com o rápido crescimento da complexidade dos circuitos fabricados, a geração de testes passou a ser um sério problema para a indústria de circuitos integrados. Muitos algoritmos de ATPG (Automatic Test Pattern Generation) baseados no algoritmo D, usam heurísticas para guiar o processo de tomada de decisão na propagação n e na justificação das constantes de forma a aumentar sua eficiencia. Existem heurísticas baseadas em medidas funcionais, estruturais e probabilísticas. Estas medidas são normalmente referidas como observabilidade e controlabilidade que fazem parte de um conceito mais geral, a testabilidade. As medidas que o algoritmo utiliza podem ser calculadas apenas uma vez, durante uma etapa de pré-processamento (medidas de testabilidade estáticas - STM's), ou dinamicamente, recalculando estas medidas durante o processamento sempre que elas forem necessárias (medidas de testabilidade dinâmicas — DTM's). Para alguns circuitos, o use de medidas dinâmicas ao invés de medidas estáticas diminui o número de backtrackings pcir vetor gerado. Apesar disto, o tempo total de CPU por vetor aumenta. Assim, as DTM's só devem ser utilizadas quando as STM's não apresentam uma boa performance. Isto pode ser feito utilizando-se as medidas estáticas ate um certo número de backtrackings. Se o padrão de teste não for encontrado, então medidas dinâmicas são utilizadas. Entretanto, a necessário ainda buscar formas de melhorar o processo dinâmico, diminuindo o custo computacional. A proposta original do calculo das DTM's apresenta algumas técnicas, baseadas em selective tracing, com o objetivo de reduzir o custo computacional. Este trabalho analisa o use combinado de heurísticas e propõe técnicas alternativas, na forma das heurísticas de recalculo parcial e recalculo de linhas não free, que visam minimizar o overhead do calculo das DTM's. E proposta ainda a técnica de Pré-implicação que transfere a complexidade do algoritmo para a memória. Isto é feito através de um preprocessamento que armazena informações necessárias para a geração de todos os vetores de teste. De outra forma estas informações teriam de ser calculadas na geração de cada um destes vetores. A implementação do algoritmo D com as várias heurísticas permitiu a realização de um experimento pratico. Isto possibilitou a análise quantitativa da performance do algoritmo D para vários tipos de circuitos e demonstrou a eficiência de uma das heurísticas propostas neste trabalho. / The test generation for combinational circuits that contain reconvergence is a NP-complete problem. With the rapid increase in the complexity of the fabricated circuits, the generation of test patterns poses a serious problem to the IC industry. A number of existing ATPG algorithms based on the D algorithm use heuristics to guide the decision process in the D-propagation and justification to improve the efficiency. The heuristics used by ATPG algorithm are based on structural, functional and probabilistics measures. These measures are commonly referred to as line controllability and observability and they are combined under the , more general notion of testability. The measures used by ATPG algorithms can be computed only once, during a preprocessing stage (static testability measures - STM's) or can be calculated dinamically, updating the testability measures during the test generation process (dymanic testability measures - DTM's). For some circuits, replacing STM's by DTM's decreases the average number of backtrackings per generated vector. Despite these decrease, the total CPU time per generated vector is greater when using DTM's instead of STM's. So, DTM's only must be used if the STM's don't present a good performance. This can be done by STM's until a certain number of backtrackings. If a test pattern has still not been found, then DTM's are used. Therefore, it is yet necessary to search for ways to improve the dynamic process and decrease the CPU time requirements. In the original approach some techniques for reducing the computational overhead of DTM's based on the well-know technique of selective path tracing are presented. In this work, the combined use of heuristics are analised and alternative techniques — the heuristics of partial recalculus and not free lines recalculus — are proposed. These alternative techniques were developed in order to minimize the overhead of the DTM's calculus. It is yet proposed the pre-implication technique which transfers to memory the algorithm complexity. It includes a preprocessing stage which storages all necesary informations to the generation of all test vectors. So, these informations don't need be computed in the generation of each test vector. The implementation of the D-Algorithm with diferent heuristics has possibilited a practical experiment. It was possible to analise the performance of the D-Algorithm on diferent circuit types and to demonstrate the efficiency of one of the proposed heuristics.