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In humans, damage to the mammillothalamic tract (MTT) as a result of localised strokes, tumours or alcohol abuse has consistently been implicated in the severe anterograde amnesia evident in these patients. This small neural pathway, which connects the mammillary bodies (MB) to the anterior thalamic nuclei (ATN), is thought to provide one important link in a larger extended hippocampal circuit involved in encoding and retrieval of episodic memory. Brain damage in clinical cases is, however, typically diffuse and contributions from additional sites of pathology cannot be ruled out. There are also inconsistencies within a limited animal literature on MTT lesions. The current study made MTT lesions in female rats and used multiple „episodic - like‟ memory tasks relevant to the proposed importance of this pathway. The project also intended to test whether enrichment reduces any impairments after MTT lesions. None of the lesions resulted in complete bilateral disconnection of the MTT, but many had moderate to large bilateral (n = 6) (81% to 50%), or unilateral MTT damage (n = 4). Rats with bilateral lesions were compared to controls (n = 14, including 4 other lesion rats in which no lesion occurred). The severe working memory deficit in the water maze expected for rats with MTT lesion was not found and only a slight deficit in reference memory in the water maze was observed (so enrichment was not implemented). Although none of the bilateral MTT lesions were complete, they are also often incomplete in clinical cases and previous research has shown that lesions to the ATN in excess of 50% are sufficient to induce severe behavioural deficits in rats. Therefore, if the MTT is critical to memory then substantial but not total bilateral disconnection should be sufficient to induce profound deficits in rats, at least on spatial working memory. Taken together these findings suggest a less crucial role for the MTT in memory than previously suggested. Future research needs to resolve the inconsistencies observed in the animal literature by repeating the present study, using larger MTT lesions and both male and female rats.

Ventricular fibrillation is one of the leading causes for Sudden Cardiac Death and is characterized by multiple activation wavefronts. Multiple activation wavefronts originate from a reentrant circuit which requires the presence of a unidirectional block in the path of a propagating excitation wave. It has been proposed that at the cellular level beat to beat alternation in the action potential duration at rapid pacing rates can result in a conduction block. Various mechanisms have been postulated to show the mechanisms of alternans. We use simulated activation in a one dimensional tissue fiber to show the existence of a new mechanism via which alternans can result. We used a new pacing protocol to eliminate alternans at the pacing site, and thus eliminating restitution of action potential duration at this site to reveal existence of alternans down the fiber. Effects on alternans of manipulations of specific ionic currents such as the sodium current (INa), calcium current (ICaL), potassium current (Ikr) and of the diffusion co-efficient (Dx) which simulates reduced expression of connexin 43 were determined. Decrease in sodium conductance, i.e. in excitability by half caused the alternans to occur at the pacing site itself even though APD restitution was eliminated. An increase or decrease in calcium current (ICaL) eliminated alternans throughout the fiber. The use of a novel pacing approach in investigation of alternans, as in this study, furthers our understanding of the mechanism of alternans and may prove helpful in the development of better anti-arrhythmic drugs in the future.

Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when optimizing a design for speed, power, etc. These characteristics affect the bottom line when considering an integrated circuit used in a particular application. In order for there to be an under- standing of device physics, there must be a device model that is developed for a device of interest. The development of a device model often involves utilizing fundamental physical equations in a manner that is solvable by either analytical or numerical means. This typically begins by simplifying fundamental physical equations, possibly spanning multiple domains, and considering the physical quantities of interest. In order to make simplifications, assumptions about the underlying physics must be made. It is the process of transitioning from known physics laws to simplified mathematical models that a device modeler spans. This thesis will cover the device modeling aspects of a new classification of computing devices, spintronics. It will begin by stating the physical assumptions necessary for the operation of spintronic devices. Then it will go the process of deriving the underlying physical equations and stating them in a tractable form with the appropriate boundary conditions. Then these equations will be manipulated and mapped into an equivalent circuit. The equivalent circuits will them be validated against analytical solutions provided from other works. It will then finish by providing example devices that can be simulated with the develop device models, and some optimization results are proposed based off a simplified circuit model.

Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.

The development of high temperature heat exchangers will play a vital part in the success of High Temperature Nuclear Reactors (HTRs). Manufacturing such heat exchangers from metals is becoming increasingly difficult as the operating temperatures keep rising. Above 1000'C most metals loose their strength and have high creep rates, while certain ceramic materials (including graphite, in the absence of oxygen) are able to operate at these temperatures. A literature study was done in order to identify the major problems regarding the use of graphite for heat exchanger construction as well as to investigate to what extent graphite has been used for heat exchanger construction in the past. Following from the literature survey, it was decided to design and manufacture a Printed Circuit Heat Exchanger (PCHE) from isotropic graphite to gain experience regarding the use of graphite as a heat exchanger material. This heat exchanger was then tested in order to learn about the operation of a graphite heat exchanger and to determine its effectiveness. A model ofthe heat exchanger was also constructed in order to determine what the performance of such a heat exchanger should theoretically be. It was found that the single greatest hurdle standing in the way ofgraphite being used as a heat exchanger material is its high gas permeability. This causes mixing between the two fluid streams as well as leakages to the environment, which have a negative effect on the heat exchanger's heat transfer capability. The methods used to establish a seal between the consecutive plates of the PCHE are also affected by the permeability of the graphite. Coatings on the surface of the graphite might be able to reduce its permeability and can also inhibit the high temperature degradation of graphite in the presence of oxygen. Manufacturing very small flow channels for the PCHE is limited by the availability of small enough end mills. Alternative manufucturing techniques is needed to economically construct a graphite PCHE. It was also found that the heat transfer effectiveness of the heat exchanger is influenced negatively by heat losses to the environment through the outer surface ofthe heat exchanger. Effective insulation around the heat exchanger or a graphite material :vith higher heat conductivity perpendicular to the flow direction might solve this problem. This study concluded that if diffusion bonding techniques, effective coatings and a graphite material with increased heat conductivity perpendicular to the flow direction are used, manufacturing a printed circuit heat exchanger from graphite is feasible. / Thesis (M.Ing. (Nuclear Engineering))--North-West University, Potchefstroom Campus, 2010

This thesis describes a new approach to accelerate the simulation of the steady-state response of nonlinear circuits using the Harmonic Balance (HB) technique. The approach presented in this work focuses on direct factorization of the sparse Jacobian matrix of the HB nonlinear equations using a Graphics Processing Unit (GPU) platform. This approach exploits the heterogeneous structure of the Jacobian matrix. The computational core of the proposed approach is based on developing a block-wise version of the KLU factorization algorithm, where scalar arithmetic operations are replaced by block-aware matrix operations. For a large number of harmonics, or excitation tones, or both the Block-KLU (BKLU) approach effectively raises the ratio of floating-point operations to other operations and, therefore, becomes an ideal vehicle for implementation on a GPU-based platform. Motivated by this fact, a GPU-based Hybrid Block KLU framework is developed to implement the BKLU. The proposed approach in this thesis is named Hybrid-BKLU. The Hybrid-BKLU is implemented in two parts, on the host CPU and on the graphic card’s GPU, using the OpenCL heterogeneous parallel programming language. To show the efficiency of the Hybrid-BKLU approach, its performance is compared with BKLU approach performing HB analysis on several test circuits. The Hybrid-BKLU approach yields speedup by up to 89 times over conventional BKLU on CPU.