Thesis (M.S. in Electrical Engineering)--Washington State University. / Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

No description available.

No description available.

Clock skew caused by variation is one of the most important problems in clock network synthesis today. Even if a clock network is designed to have zero skew, variation such as capacitive load and power supply will cause differences in arrival time of a clock signal. Non-tree clock network is considered to be an effective way to address the skew variation problem. Due to its inherent redundancy, clock mesh is very tolerant to variation. However, it costs much excessive amount of power compared to a clock tree. Link based non-tree clock network is an economic way to reduce clock skew caused by variation. Instead of using a dense mesh, only a number of links are inserted into a tree, so the power increase is small. Several existing works focus on the effect of cross link as well as the construction of such cross link structure. However, it is still not very clear where cross links should be inserted to achieve the most clock skew reduction with small wire resources. In this thesis, we propose a new method using linear program to solve this problem. In our approach, clock skew in a non-tree clock network is computed using an idea of load redistribution and non-tree decomposition. The delay information obtained is then used to select the node pairs for cross link insertion. Our methodology tries to insert cross links where skew can be reduced most effectively. Our method also considers tradeoff between cross link length and skew reduction effect. We compare our result with the most similar work on this problem [1] and a recent work [4] which inserts links between internal nodes of a tree. Experiments show that our method can reduce skew under variation effectively. We achieve 28% clock skew reduction with only 40% link resources. / Qian, Fuqiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 51-55). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Clock Distribution Network --- p.1 / Chapter 1.2 --- Our Contributions --- p.6 / Chapter 1.3 --- Organization of the Thesis --- p.8 / Chapter 2 --- Literature Review --- p.9 / Chapter 2.1 --- Exact Zero Skew --- p.9 / Chapter 2.2 --- DME Algorithm --- p.11 / Chapter 2.3 --- Combinatorial Algorithms for Fast Clock Mesh Optimization --- p.12 / Chapter 2.4 --- MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks --- p.14 / Chapter 2.5 --- Reducing Clock Skew variability via Cross Links --- p.16 / Chapter 2.6 --- Statistical Based Link Insertion for Robust Clock Network Design --- p.18 / Chapter 2.7 --- Variation Tolerant Buffered Clock Network Synthesis with Cross Links --- p.20 / Chapter 2.8 --- Cross Link Insertion for Improving Tolerance to Variations in Clock Network Synthesis --- p.22 / Chapter 3 --- Clock Network Construction with Cross Links --- p.24 / Chapter 3.1 --- Signal Delay and Clock Skew in Non-tree Clock Network --- p.24 / Chapter 3.1.1 --- Computing Delay in Non-tree Network --- p.25 / Chapter 3.1.2 --- Effect of a Cross Link on Clock Skew --- p.27 / Chapter 3.2 --- Link Insertion for Non-tree Clock Network --- p.28 / Chapter 3.2.1 --- Motivation of Computing Delay for Link Insertion --- p.29 / Chapter 3.2.2 --- Overall Flow for Cross Link Insertion --- p.30 / Chapter 3.2.3 --- Linear Program for Selecting Node Pairs --- p.31 / Chapter 3.2.4 --- Reducing the Number of Optimizations --- p.35 / Chapter 3.2.5 --- Experimental Results --- p.37 / Chapter 4 --- Buffered Clock Network with Cross Links --- p.41 / Chapter 4.1 --- Link Insertion in Buffered Clock Network --- p.41 / Chapter 4.1.1 --- Delay Calculation in Buffered Clock Network --- p.42 / Chapter 4.1.2 --- Linear Program Formulation for Buffered Clock Network --- p.43 / Chapter 4.2 --- Experimental Results and Comparison --- p.44 / Chapter 4.3 --- Possible Extensions --- p.46 / Chapter 4.3.1 --- Link Insertion at Internal Nodes --- p.46 / Chapter 4.3.2 --- Modeling Clock Buffer Delay Variation --- p.47 / Chapter 5 --- Conclusion --- p.49 / Bibliography --- p.51

Thesis (M.S.)--Ohio University, November, 1999. / Title from PDF t.p.

Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 55-57). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Rhode Island, 2003. / Typescript. Includes bibliographical references (leaves 87-93).

Thesis (Ph. D.)--University of Rhode Island, 2003. / Typescript. Includes bibliographical references (leaves 174-184).

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 75-77). Also available on the World Wide Web.