by Cheng King Sum Frankie. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaf 53). / Acknowledgments --- p.iv / List of Figures --- p.vii / List of Tables --- p.ix / Abstract --- p.x / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Multiple Clock System --- p.1 / Chapter 1.2 --- Clock Multiplier --- p.2 / Phase-Locked Loop --- p.2 / Delay Locked Loop --- p.3 / Chapter 1.3 --- Objective --- p.5 / Chapter Chapter2 --- All-Digital Clock Multiplier --- p.6 / Chapter 2.1 --- Architecture --- p.6 / Chapter 2.2 --- Operation --- p.7 / Chapter 2.3 --- Implementation --- p.9 / Control Circuit --- p.9 / Phase-Locked Circuit --- p.11 / Frequency Detector --- p.12 / Frequency Divider --- p.13 / Synchronize Logic --- p.14 / DCO Control --- p.15 / Chapter Chapter3 --- Digitally-Controlled Oscillator --- p.16 / Chapter 3.1 --- Principle --- p.16 / Chapter 3.2 --- Design --- p.18 / Transient Analysis --- p.18 / Simulation result --- p.26 / Chapter 3.3 --- Layout --- p.30 / Chapter 3.4 --- Summary --- p.32 / Chapter Chapter4 --- Test and Measurement --- p.34 / Chapter 4.1 --- Digitally-Controlled Oscillator Characteristics --- p.34 / Chapter 4.2 --- All-Digital Clock Multiplier Characteristics --- p.43 / Chapter Chapter5 --- Conclusions --- p.51 / Chapter 5.1 --- Summary --- p.51 / Chapter 5.2 --- Recommendation for Future Work --- p.52 / References --- p.53 / Appendix A --- p.54 / Publications and Presentations --- p.54

by Johnson, Tin-Chak Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references. / Acknowledgments / Abstract / List of figures / List of tables / Chapter 1. --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Introduction to asynchronous system --- p.1-5 / Chapter 1.2.1 --- Motivation --- p.1-5 / Chapter 1.2.2 --- Hazards --- p.1-7 / Chapter 1.2.3 --- Classes of Asynchronous circuits --- p.1-8 / Chapter 1.3 --- Introduction to Transform Coding --- p.1-9 / Chapter 1.4 --- Organization of the Thesis --- p.1-16 / Chapter 2. --- Asynchronous Design Methodologies --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Self-timed system --- p.2-2 / Chapter 2.3 --- DCVSL Methodology --- p.2-4 / Chapter 2.3.1 --- DCVSL gate --- p.2-5 / Chapter 2.3.2 --- Handshake Control --- p.2-7 / Chapter 2.4 --- Micropipeline Methodology --- p.2-11 / Chapter 2.4.1 --- Summary of previous design --- p.2-12 / Chapter 2.4.2 --- New Micropipeline structure and improvements --- p.2-17 / Chapter 2.4.2.1 --- Asymmetrical delay --- p.2-20 / Chapter 2.4.2.2 --- Variable Delay and Delay Value Selection --- p.2-22 / Chapter 2.5 --- Comparison between DCVSL and Micropipeline --- p.2-25 / Chapter 3. --- Self-timed Multipliers --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Design Example 1 : Bit-serial matrix multiplier --- p.3-3 / Chapter 3.2.1 --- DCVSL design --- p.3-4 / Chapter 3.2.2 --- Micropipeline design --- p.3-4 / Chapter 3.2.3 --- The first test chip --- p.3-5 / Chapter 3.2.4 --- Second test chip --- p.3-7 / Chapter 3.3 --- Design Example 2 - Modified Booth's Multiplier --- p.3-9 / Chapter 3.3.1 --- Circuit Design --- p.3-10 / Chapter 3.3.2 --- Simulation result --- p.3-12 / Chapter 3.3.3 --- The third test chip --- p.3-14 / Chapter 4. --- Current-Sensing Completion Detection --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Current-sensor --- p.4-2 / Chapter 4.2.1 --- Constant current source --- p.4-2 / Chapter 4.2.2 --- Current mirror --- p.4-4 / Chapter 4.2.3 --- Current comparator --- p.4-5 / Chapter 4.3 --- Self-timed logic using CSCD --- p.4-9 / Chapter 4.4 --- CSCD test chips and testing results --- p.4-10 / Chapter 4.4.1 --- Test result --- p.4-11 / Chapter 5. --- Self-timed ICT processor architecture --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Comparison of different architecture --- p.5-3 / Chapter 5.2.1 --- General purpose Digital Signal Processor --- p.5-5 / Chapter 5.2.1.1 --- Hardware and speed estimation : --- p.5-6 / Chapter 5.2.2 --- Micropipeline without fast algorithm --- p.5-7 / Chapter 5.2.2.1 --- Hardware and speed estimation : --- p.5-8 / Chapter 5.2.3 --- Micropipeline with fast algorithm (I) --- p.5-8 / Chapter 5.2.3.1 --- Hardware and speed estimation : --- p.5-9 / Chapter 5.2.4 --- Micropipeline with fast algorithm (II) --- p.5-10 / Chapter 5.2.4.1 --- Hardware and speed estimation : --- p.5-11 / Chapter 6. --- Implementation of self-timed ICT processor --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Implementation of Self-timed 2-D ICT processor (First version) --- p.6-3 / Chapter 6.2.1 --- 1-D ICT module --- p.6-4 / Chapter 6.2.2 --- Self-timed Transpose memory --- p.6-5 / Chapter 6.2.3 --- Layout Design --- p.6-8 / Chapter 6.3 --- Implementation of Self-timed 1-D ICT processor with fast algorithm (final version) --- p.6-9 / Chapter 6.3.1 --- I/O buffers and control units --- p.6-10 / Chapter 6.3.1.1 --- Input control --- p.6-11 / Chapter 6.3.1.2 --- Output control --- p.6-12 / Chapter 6.3.1.2.1 --- Self-timed Computational Block --- p.6-13 / Chapter 6.3.1.3 --- Handshake Control Unit --- p.6-14 / Chapter 6.3.1.4 --- Integer Execution Unit (IEU) --- p.6-18 / Chapter 6.3.1.5 --- Program memory and Instruction decoder --- p.6-20 / Chapter 6.3.2 --- Layout Design --- p.6-21 / Chapter 6.4 --- Specifications of the final version self-timed ICT chip --- p.6-22 / Chapter 7. --- Testing of Self-timed ICT processor --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Pin assignment of Self-timed 1 -D ICT chip --- p.7-2 / Chapter 7.3 --- Simulation --- p.7-3 / Chapter 7.4 --- Testing of Self-timed 1-D ICT processor --- p.7-5 / Chapter 7.4.1 --- Functional test --- p.7-5 / Chapter 7.4.1.1 --- Testing environment and results --- p.7-5 / Chapter 7.4.2 --- Transient Characteristics --- p.7-7 / Chapter 7.4.3 --- Comments on speed and power --- p.7-10 / Chapter 7.4.4 --- Determination of optimum delay control voltage --- p.7-12 / Chapter 7.5 --- Testing of delay element and other logic cells --- p.7-13 / Chapter 8. --- Conclusions --- p.8-1 / Bibliography / Appendices

Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates based on a decision-directed device. Timing recovery performance is a strong function of the reliability of decisions, and hence, of the channel signal-to-noise ratio (SNR). Iteratively decodable error-control codes (ECCs) like turbo codes and LDPC codes allow operation at SNRs lower than ever before, thus exacerbating timing recovery. We propose iterative timing recovery, where the timing recovery block, the equalizer and the ECC decoder exchange information, giving the timing recovery block access to decisions that are much more reliable than the instantaneous ones. This provides significant SNR gains at a marginal complexity penalty over a conventional turbo equalizer where the equalizer and the ECC decoder exchange information. We also derive the Cramer-Rao bound, which is a lower bound on the estimation error variance of any timing estimator, and propose timing recovery methods that outperform the conventional PLL and achieve the Cramer-Rao bound in some cases. At low SNR, timing recovery suffers from cycle slips, where the receiver drops or adds one or more symbols, and consequently, almost always the ECC decoder fails to decode. Iterative timing recovery has the ability to corrects cycle slips. To reduce the number of iterations, we propose cycle slip detection and correction methods. With iterative timing recovery, the PLL with cycle slip detection and correction recovers most of the SNR loss of the conventional receiver that separates timing recovery and turbo equalization.

A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage.

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 93-95). Also available in electronic format on the Internet.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

[EN] Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals. The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one. As a first step, a general study of DAQ arquitectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards. Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the particular case of two detectors. This DAQ is finally installed at the experimental setup, where their synchronization properties and resolution as a PET system are characterized and its performance is verified to have improved with respect to the previous system. / [ES] La Tomografía por Emisión de Positrones (PET) es una modalidad de imagen médica nuclear no invasiva que permite observar la distribución de sustancias metabólicas en el interior del cuerpo de un paciente tras marcarlas con isótopos radioactivos y disponer después un escáner anular a su alrededor para detectar su desintegración. Las principales aplicaciones de esta técnica son la detección y seguimiento de tumores en pacientes con cáncer y los estudios metabólicos en animales pequeños. El grupo de investigación Electronic Design for Nuclear Applications (EDNA) del Instituto de Instrumentación para Imagen Molecular (I3M) ha estado involucrado en el estudio de sistemas PET de alto rendimiento y mantiene un pequeño setup experimental con dos módulos detectores. La presente tesis se enmarca dentro de la necesidad de desarrollar un nuevo sistema de adquisición de datos (DAQ) para dicho setup que corrija los inconvenientes del ya existente. En particular, el objetivo es definir una arquitectura de DAQ que sea totalmente escalable, modular, y que asegure la movilidad y la posibilidad de reutilización de sus componentes, de manera que admita cualquier ampliación o alteración del setup y pueda exportarse directamente a los de otros grupos o experimentos. Al mismo tiempo, se desea que dicha arquitectura no limite artificialmente el rendimiento del sistema sino que sea compatible con las mejores resoluciones disponibles en la actualidad, y en particular que sus prestaciones superen a las del DAQ instalado previamente. En primer lugar, se lleva a cabo un estudio general de las arquitecturas de DAQ para setups experimentales para PET y otras aplicaciones de física de altas energías. Por un lado, se determina que las características deseadas implican la digitalización temprana de las señales del detector, la comunicación exclusivamente digital entre módulos, y la ausencia de trigger centralizado. Por otro lado, se hace patente la necesidad de un esquema de sincronización distribuida muy preciso entre módulos, con errores del orden de 100 ps, que opere directamente sobre los enlaces de datos. Un estudio de los métodos ya existentes revela sus graves limitaciones a la hora de alcanzar esas precisiones. Con el fin de paliarlos, se lleva a cabo un análisis teórico de la situación y se propone un nuevo algoritmo de sincronización que es capaz de alcanzar la resolución deseada y elimina las restricciones de alineamiento de reloj impuestas por casi todos los esquemas usuales. Dado que la medida de desfase entre relojes juega un papel crucial en el algoritmo propuesto, se definen y analizan extensiones a los métodos ya existentes que suponen una mejora sustancial. El esquema de sincronismo propuesto se valida utilizando placas de evaluación comerciales. Partiendo del método de sincronismo propuesto, se define una arquitectura de DAQ para PET compuesta de dos tipos de módulos (adquisición y concentración) cuya replicación permite construir un sistema jerárquico de tamaño arbitrario, y se diseñan e implementan placas de circuito basadas en dicha arquitectura para el caso particular de dos detectores. El DAQ así construído se instala finalmente en el setup experimental, donde se caracterizan tanto sus propiedades de sincronización como su resolución como sistema PET y se comprueba que sus prestaciones son superiores a las del sistema previo. / [CA] La Tomografia per Emissió de Positrons (PET) és una modalitat d'imatge mèdica nuclear no invasiva que permet observar la distribució de substàncies metabòliques a l'interior del cos d'un pacient després d'haver-les marcat amb isòtops radioactius disposant un escàner anular al seu voltant per a detectar la seua desintegració. Aquesta tècnica troba les seues principals aplicacions a la detecció i seguiment de tumors a pacients amb càncer i als estudis metabòlics en animals petits. El grup d'investigació Electronic Design for Nuclear Applications (EDNA) de l'Instituto de Instrumentación para Imagen Molecular (I3M) ha estat involucrat en l'estudi de sistemes PET d'alt rendiment i manté un petit setup experimental amb dos mòduls detectors. Aquesta tesi neix de la necessitat de desenvolupar un nou sistema d'adquisició de dades (DAQ) per al setup esmentat que corregisca els inconvenients de l'anterior. En particular, l'objectiu és definir una arquitectura de DAQ que sigui totalment escalable, modular, i que asseguri la mobilitat i la possibilitat de reutilització dels seus components, de tal manera que admeta qualsevol ampliació o alteració del setup i pugui exportar-se directament a aquells d'altres grups o experiments. Al mateix temps, es desitja que aquesta arquitectura no introduisca límits artificials al rendiment del sistema sinó que sigui compatible amb les millors resolucions disponibles a l'actualitat, i en particular que les seues prestacions siguin superiors a les del DAQ instal.lat amb anterioritat. En primer lloc, es porta a terme un estudi general de les arquitectures de DAQ per a setups experimentals per a PET i altres aplicacions de física d'altes energies. Per una banda, s'arriba a la conclusió que les característiques desitjades impliquen la digitalització dels senyals del detector el més aviat possible, la comunicació exclusivament digital entre mòduls, i l'absència de trigger centralitzat. D'altra banda, es fa palesa la necessitat d'un mecanisme de sincronització distribuïda molt precís entre mòduls, amb errors de l'ordre de 100 ps, que treballi directament sobre els enllaços de dades. Un estudi dels mètodes ja existents revela les seues greus limitacions a l'hora d'assolir aquest nivell de precisió. Amb l'objectiu de pal.liar-les, es duu a terme una anàlisi teòrica de la situació i es proposa un nou algoritme de sincronització que és capaç d'obtindre la resolució desitjada i es desfà de les restriccions d'alineament de rellotges imposades per gairebé tots els esquemes usuals. Atès que la mesura del desfasament entre rellotges juga un paper cabdal a l'algoritme proposat, es defineixen i analitzen extensions als mètodes ja existents que suposen una millora substancial. L'esquema de sincronisme proposat es valida mitjançant plaques d'avaluació comercials. Prenent el mètode proposat com a punt de partida, es defineix una arquitectura de DAQ per a PET composta de dos tipus de mòduls (d'adquisició i de concentració) tals que la replicació d'aquests elements permet construir un sistema jeràrquic de mida arbitrària, i es dissenyen i implementen plaques de circuit basades en aquesta arquitectura per al cas particular de dos detectors. L'electrònica desenvolupada s'instal.la finalment al setup experimental, on es caracteritzen tant les seues propietats de sincronització com la seua resolució com a sistema PET i es comprova que les seues prestacions són superiors a les del sistema previ. / Aliaga Varea, RJ. (2016). Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63271 / TESIS / Premios Extraordinarios de tesis doctorales