Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "November 2006." Includes bibliographical references (leaves 121-124). Also available via the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 118-126). Available also in a digital version from Dissertation Abstracts.

by Eva Yuk-Wah Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 88-89). / ACKNOWLEDGEMETS / ABSTRACT / LIST OF FIGURES / LIST OF TABLES / Chapter CHAPTER1 --- INTRODUCTION / Chapter 1.1 --- Motivation --- p.1-1 / Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1 / Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2 / Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3 / Chapter 1.2 --- Overview of the Thesis --- p.1-5 / Chapter CHAPTER2 --- BACKGROUND / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Models for Asynchronous System --- p.2-2 / Chapter 2.2.1 --- Huffman model --- p.2-2 / Chapter 2.2.2 --- Muller model --- p.2-4 / Chapter 2.3 --- Self-timed System --- p.2-5 / Chapter 2.3.1 --- Definitions and Assumptions --- p.2-6 / Chapter 2.4 --- Design Methodologies --- p.2-8 / Chapter 2.4.1 --- Differential Logic Structure Design Methodology --- p.2-9 / Chapter 2.4.1.1 --- Data Path --- p.2-9 / Chapter 2.4.1.2 --- Control Path --- p.2-10 / Chapter 2.4.2 --- Micropipeline Design Methodology --- p.2-12 / Chapter 2.4.2.1 --- Data Path --- p.2-12 / Chapter 2.4.2.2 --- Control Path --- p.2-13 / Chapter CHAPTER3 --- SELF-TIMED CELL LIBRARY / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Muller C element --- p.3-1 / Chapter 3.3 --- Differential Cascode Voltage Switch Logic Circuits --- p.3-6 / Chapter 3.3.1 --- INVERTER --- p.3-8 / Chapter 3.3.2 --- "AND, OR, NAND, NOR" --- p.3-8 / Chapter 3.3.3 --- "XOR, XNOR" --- p.3-10 / Chapter 3.4 --- Latches --- p.3-11 / Chapter 3.4.1 --- Precharged Latch --- p.3-12 / Chapter 3.4.2 --- Capture and Pass Latch --- p.3-12 / Chapter 3.5 --- Delay Elements --- p.3-13 / Chapter 3.6 --- Discussion --- p.3-15 / Chapter CHAPTER4 --- THE CHARACTERISTICS OF SELF-TIMED CELL LIBRARY / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- The Simulation Characteristics --- p.4-2 / Chapter 4.2.1 --- HSPICE program --- p.4-2 / Chapter 4.2.2 --- Characterization Information and Datasheet terms --- p.4-5 / Chapter 4.2.3 --- Characterization values --- p.4-6 / Chapter 4.3 --- The Experimental Analysis --- p.4-6 / Chapter 4.4 --- Experimental Result and Discussion --- p.4-9 / Chapter 4.4.1 --- Experimental Result --- p.4-9 / Chapter 4.4.2 --- Comparison of the characteristics of C-elements --- p.4-12 / Chapter 4.4.3 --- Comparison of simulation with experimental results --- p.4-13 / Chapter 4.4.4 --- Properties of DCVSL gate --- p.4-14 / Chapter 4.4.5 --- The Characteristics of Delay elements --- p.4-15 / Chapter 4.5 --- CAD Features on Cadence --- p.4-16 / Chapter CHAPTER5 --- DESIGN EXAMPLE: SELF-TIMED MATRIX MULTIPLIER / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- A Matrix Multiplier using DCVSL structure --- p.5-2 / Chapter 5.2.1 --- Structure --- p.5-2 / Chapter 5.2.2 --- Handshaking Control Circuit --- p.5-3 / Chapter 5.2.2.1 --- Handshaking Control Circuit of Pipeline --- p.5-4 / Chapter 5.2.2.2 --- Handshaking Control Circuit of Feedback Path --- p.5-8 / Chapter 5.3 --- A Matrix Multiplier using Micropipeline Structure --- p.5-10 / Chapter 5.3.1 --- Structure --- p.5-10 / Chapter 5.3.2 --- Control Circuit --- p.5-12 / Chapter 5.4 --- Experimental Result --- p.5-13 / Chapter 5.4.1 --- The Matrix Multiplier using DCVSL structure --- p.5-13 / Chapter 5.4.2 --- The Matrix Multiplier using Micropipeline structure --- p.5-16 / Chapter 5.5 --- Comparison of DCVSL structure and Micropipeline structure --- p.5-18 / Chapter CHAPTER6 --- CONCLUSION / Chapter 6.1 --- Achievement --- p.6-1 / Chapter 6.1.1 --- Self-timed Cell Library --- p.6-1 / Chapter 6.1.2 --- Self-timed System Design simplification --- p.6-2 / Chapter 6.1.3 --- Area and Speed --- p.6-3 / Chapter 6.1.4 --- Applications --- p.6-4 / Chapter 6.2 --- Future work --- p.6-6 / Chapter 6.2.1 --- Interface with synthesis tools --- p.6-6 / Chapter 6.2.2 --- Mixed Circuit Design --- p.6-6 / REFERENCES / APPENDICES

Tong Ka Yau Dennis. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 77-81). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background on Retiming --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Preliminaries --- p.7 / Chapter 2.3 --- Retiming Problem --- p.9 / Chapter 3 --- Literature Review on Retiming --- p.10 / Chapter 3.1 --- Introduction --- p.10 / Chapter 3.2 --- The First Retiming Paper --- p.11 / Chapter 3.2.1 --- """Retiming Synchronous Circuitry""" --- p.11 / Chapter 3.3 --- Important Extensions of the Basic Retiming Algorithm --- p.14 / Chapter 3.3.1 --- """A Fresh Look at Retiming via Clock Skew Optimization""" --- p.14 / Chapter 3.3.2 --- """An Improved Algorithm for Minimum-Area Retiming""" --- p.16 / Chapter 3.3.3 --- """Efficient Implementation of Retiming""" --- p.17 / Chapter 3.4 --- Retiming in Physical Design Stages --- p.19 / Chapter 3.4.1 --- """Physical Planning with Retiming""" --- p.19 / Chapter 3.4.2 --- """Simultaneous Circuit Partitioning/Clustering with Re- timing for Performance Optimization" --- p.20 / Chapter 3.4.3 --- """Performance Driven Multi-level and Multiway Parti- tioning with Retiming" --- p.22 / Chapter 3.5 --- Retiming with More Sophisticated Timing Models --- p.23 / Chapter 3.5.1 --- """Retiming with Non-zero Clock Skew, Variable Register, and Interconnect Delay""" --- p.23 / Chapter 3.5.2 --- """Placement Driven Retiming with a Coupled Edge Tim- ing Model""" --- p.24 / Chapter 3.6 --- Post-Retiming Register Placement --- p.26 / Chapter 3.6.1 --- """Layout Driven Retiming Using the Coupled Edge Tim- ing Model""" --- p.26 / Chapter 3.6.2 --- """Integrating Logic Retiming and Register Placement""" --- p.27 / Chapter 4 --- Retiming with Gate and Wire Delay [2] --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Problem Formulation --- p.30 / Chapter 4.3 --- Optimal Approach [2] --- p.31 / Chapter 4.3.1 --- Original Mathematical Framework for Retiming --- p.31 / Chapter 4.3.2 --- A Modified Optimal Approach --- p.33 / Chapter 4.4 --- Near-Optimal Fast Approach [2] --- p.37 / Chapter 4.4.1 --- Considering Wire Delay Only --- p.38 / Chapter 4.4.2 --- Considering Both Gate and Wire Delay --- p.42 / Chapter 4.4.3 --- Computational Complexity --- p.43 / Chapter 4.4.4 --- Experimental Results --- p.44 / Chapter 4.5 --- Lin's Optimal Approach [23] --- p.47 / Chapter 4.5.1 --- Theoretical Results --- p.47 / Chapter 4.5.2 --- Algorithm Description --- p.51 / Chapter 4.5.3 --- Computational Complexity --- p.52 / Chapter 4.5.4 --- Experimental Results --- p.52 / Chapter 4.6 --- Summary --- p.54 / Chapter 5 --- Register Insertion in Placement [36] --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.57 / Chapter 5.3 --- Placement of Registers After Retiming --- p.60 / Chapter 5.3.1 --- Topology Finding --- p.60 / Chapter 5.3.2 --- Register Placement --- p.69 / Chapter 5.4 --- Experimental Results --- p.71 / Chapter 5.5 --- Summary --- p.74 / Chapter 6 --- Conclusion --- p.75 / Bibliography --- p.77

由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。 / 為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。 / With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience. / To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yuan, Feng. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 88-100). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2 / Chapter 1.2 --- Contributions and Thesis Outline --- p.5 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- Sources of Timing Uncertainty --- p.7 / Chapter 2.1.1 --- Process Variation --- p.7 / Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9 / Chapter 2.1.3 --- Aging Effect --- p.10 / Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10 / Chapter 2.3 --- False Path --- p.12 / Chapter 2.3.1 --- Path Sensitization Criteria --- p.12 / Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13 / Chapter 2.4 --- Manufacturing Testing --- p.14 / Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14 / Chapter 2.4.2 --- Scan-Based DfT --- p.15 / Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17 / Chapter 2.5 --- Timing Error Tolerance --- p.19 / Chapter 2.5.1 --- Timing Error Detection --- p.19 / Chapter 2.5.2 --- Timing Error Recover --- p.20 / Chapter 3 --- Timing-Independent False Path Identification --- p.23 / Chapter 3.1 --- Introduction --- p.23 / Chapter 3.2 --- Preliminaries and Motivation --- p.26 / Chapter 3.2.1 --- Motivation --- p.27 / Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28 / Chapter 3.3.1 --- Path Sensitization Criterion --- p.28 / Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30 / Chapter 3.3.3 --- Proposed Examination Procedure --- p.31 / Chapter 3.4 --- False Path Identification --- p.32 / Chapter 3.4.1 --- Overall Flow --- p.34 / Chapter 3.4.2 --- Static Implication Learning --- p.35 / Chapter 3.4.3 --- Suspicious Node Extraction --- p.36 / Chapter 3.4.4 --- S-Frontier Propagation --- p.37 / Chapter 3.5 --- Experimental Results --- p.38 / Chapter 3.6 --- Conclusion and Future Work --- p.42 / Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Preliminaries and Motivation --- p.45 / Chapter 4.2.1 --- Motivation --- p.46 / Chapter 4.3 --- Proposed Methodology --- p.48 / Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50 / Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51 / Chapter 4.5 --- Experimental Results --- p.59 / Chapter 4.5.1 --- Experimental Setup --- p.59 / Chapter 4.5.2 --- Results and Discussion --- p.60 / Chapter 4.6 --- Conclusion --- p.64 / Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Prior Work and Motivation --- p.67 / Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69 / Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70 / Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72 / Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75 / Chapter 5.4.1 --- Overall Flow --- p.76 / Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77 / Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79 / Chapter 5.5 --- Experimental Results --- p.81 / Chapter 5.5.1 --- Experimental Setup --- p.81 / Chapter 5.5.2 --- Results and Discussion --- p.82 / Chapter 5.6 --- Conclusion --- p.85 / Chapter 6 --- Conclusion and Future Work --- p.86 / Bibliography --- p.100

Tian, Haitong. / Chinese abstract is on unnumbered page. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 65-74). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Our Contributions --- p.2 / Chapter 1.3 --- Organization of the Thesis --- p.3 / Chapter 2 --- Background Study --- p.4 / Chapter 2.1 --- Traditional Clock Routing Problem --- p.4 / Chapter 2.2 --- Tree-Based Clock Routing Algorithms --- p.5 / Chapter 2.2.1 --- Clock Routing Using H-tree --- p.5 / Chapter 2.2.2 --- Method of Means and Medians(MMM) --- p.6 / Chapter 2.2.3 --- Geometric Matching Algorithm (GMA) --- p.8 / Chapter 2.2.4 --- Exact Zero-Skew Algorithm --- p.9 / Chapter 2.2.5 --- Deferred Merge Embedding (DME) --- p.10 / Chapter 2.2.6 --- Boundary Merging and Embedding (BME) Algorithm --- p.14 / Chapter 2.2.7 --- Planar Clock Routing Algorithm --- p.17 / Chapter 2.2.8 --- Useful-skew Tree Algorithm --- p.18 / Chapter 2.3 --- Non-Tree Clock Distribution Networks --- p.19 / Chapter 2.3.1 --- Grid (Mesh) Structure --- p.20 / Chapter 2.3.2 --- Spine Structure --- p.20 / Chapter 2.3.3 --- Hybrid Structure --- p.21 / Chapter 2.4 --- Post-grid Clock Routing Problem --- p.22 / Chapter 2.5 --- Limitations of the Previous Work --- p.24 / Chapter 3 --- Post-Grid Clock Routing Problem --- p.26 / Chapter 3.1 --- Introduction --- p.26 / Chapter 3.2 --- Problem Definition --- p.27 / Chapter 3.3 --- Our Approach --- p.30 / Chapter 3.3.1 --- Delay-driven Path Expansion Algorithm --- p.31 / Chapter 3.3.2 --- Pre-processing to Connect Critical ports --- p.34 / Chapter 3.3.3 --- Post-processing to Reduce Capacitance --- p.36 / Chapter 3.4 --- Experimental Results --- p.39 / Chapter 3.4.1 --- Experiment Setup --- p.39 / Chapter 3.4.2 --- Validations of the Delay and Slew Estimation --- p.39 / Chapter 3.4.3 --- Comparisons with the Tree Grow (TG) Approach --- p.41 / Chapter 3.4.4 --- Lowest Achievable Delays --- p.42 / Chapter 3.4.5 --- Simulation Results --- p.42 / Chapter 4 --- Non-tree Based Post-Grid Clock Routing Problem --- p.44 / Chapter 4.1 --- Introduction --- p.44 / Chapter 4.2 --- Handling Ports with Large Load Capacitances --- p.46 / Chapter 4.2.1 --- Problem Ports Identification --- p.47 / Chapter 4.2.2 --- Non-Tree Construction --- p.47 / Chapter 4.2.3 --- Wire Link Selection --- p.48 / Chapter 4.3 --- Path Expansion in Non-tree Algorithm --- p.51 / Chapter 4.4 --- Limitations of the Non-tree Algorithm --- p.51 / Chapter 4.5 --- Experimental Results --- p.51 / Chapter 4.5.1 --- Experiment Setup --- p.51 / Chapter 4.5.2 --- Validations of the Delay and Slew Estimation --- p.52 / Chapter 4.5.3 --- Lowest Achievable Delays --- p.53 / Chapter 4.5.4 --- Results on New Benchmarks --- p.53 / Chapter 4.5.5 --- Simulation Results --- p.55 / Chapter 5 --- Efficient Partitioning-based Extension --- p.57 / Chapter 5.1 --- Introduction --- p.57 / Chapter 5.2 --- Partition-based Extension --- p.58 / Chapter 5.3 --- Experimental Results --- p.61 / Chapter 5.3.1 --- Experiment Setup --- p.61 / Chapter 5.3.2 --- Running Time Improvement with Partitioning Technique --- p.61 / Chapter 6 --- Conclusion --- p.63 / Bibliography --- p.65

In the sub-65nm VLSI technology, the variation effects like manufacturing variation, power supply noise and temperature variation become very significant. As one of the most vital components in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. The unwanted clock skews caused by the variation effects consume increasing proportion of the clock cycle, thereby limiting chip performance and yield. Thus, making the clock network variation-tolerant is a key objective in the chip designs of today. In this dissertation, we propose several techniques that can be used to synthesize variation-tolerant clock networks. Our contributions can be broadly classified into following four categories: (i) Efficient algorithms for synthesizing link based non-tree clock networks. (ii) A methodology for synthesizing a balanced, variation tolerant, buffered clock network with cross-links. (iii) A comprehensive framework for planning, synthesis and optimization of clock mesh networks. (iv) A chip-level clock tree synthesis technique to address issues unique to hierarchical System-On-a-Chip (SOC) designs that are becoming more and more frequent today. Depending on the performance requirements and resource constraints of a given chip, the above techniques can be used separately or in combination to synthesize a variation tolerant clock network. / text

The objective of this dissertation is to develop task scheduling guidelines and algorithms for wireless sensor nodes that harvest energy from ambient environment and use supercapacitor based storage systems to buffer the harvested energy. This dissertation makes five contributions. First, a physics based equivalent circuit model for supercapacitors is developed. The variable leakage resistance (VLR) model takes into account three mechanisms of supercapacitors: voltage dependency of capacitance, charge redistribution, and self-discharge. Second, the effects of time and supercapacitor initial state on supercapacitor voltage change and energy loss during charge redistribution are investigated. Third, the task scheduling problem in supercapacitor based environmentally powered wireless sensor nodes is studied qualitatively. The impacts of supercapacitor state and energy harvesting on task scheduling are examined. Task scheduling rules are developed. Fourth, the task scheduling problem in supercapacitor based environmentally powered wireless sensor nodes is studied quantitatively. The modified earliest deadline first (MEDF) algorithm is developed to schedule nonpreemptable tasks without precedence constraints. Finally, the modified first in first out (MFIFO) algorithm is proposed to schedule nonpreemptable tasks with precedence constraints. The MEDF and MFIFO algorithms take into account energy constraints of tasks in addition to timing constraints. The MEDF and MFIFO algorithms improve the energy performance and maintain the timing performance of the earliest deadline first (EDF) and first in first out (FIFO) algorithms, respectively.

Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2009/06/08). Includes bibliographical references.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 107-110). Also available online.