No description available.

No description available.

No description available.

No description available.

Approved for public release; distribution is unlimited. / As the navy transitions to all electric warships, there will be many changes to the power distribution schemes found aboard ships today. It will be necessary to maintain reliability while supplying the various components onboard with the proper voltage levels. Since transformers cannot be used to alter voltage levels while providing galvanic isolation in DC power systems, it is necessary to find an efficient method to incorporate the increased safety provided by galvanic isolation in a DC power distribution system. This thesis examines the design and control of one possible element for a future Electrical Distribution System (EDS), a DC-DC converter with galvanic isolation. The main purpose of this study is to provide a working model with associated theoretical proof and simulations. MATLAB will be used to provide observations of the converter's operation and the success of the control scheme implemented. Future work on this topic will be assisted by the inclusion of a parts list as well as recommendations for enhancing the prospects of this technology. / Ensign, United States Navy

No description available.

The design of mixed-signal integrated circuits has evolved from simple analog and digital circuits operating on the same silicon substrate to the point that now we have complete system on a chip solutions for communication systems. The levels of integration needed to remain cost effective in today's integrated circuit (IC) market require careful use of all the available die space. The current trend of digital to analog converter (DAC) design has focused on maximizing speed and linearity for high performance telecommunications systems. The circuit design methods used to achieve very high sample rates require the use of large amounts of die space. This thesis presents a 10-bit DAC that has been optimized for area, while still maintaining accurate operation at low frequencies. To achieve 10-bit performance, an ultra high gain op-amp is introduced for various servoing applications in the DAC. The architecture chosen for the DAC will show an optimization of required die size and performance when compared to other architectures. The DAC was fabricated in a standard digital 0.18 μm CMOS process. The DAC occupies 0.0104 mm² (110 μm x 94 μm), and only consumes 2.8 mW of power. In addition to the 10-bit DAC, a design is presented for a 13-bit DAC which occupies 0.020 mm², and requires only the addition of a minimum number of devices to the 10-bit DAC. / Graduation date: 2002

Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order ����� loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio of 10. / Graduation date: 2002

A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m CMOS technology. The system is fully differential and requires two non-overlapping clock phases to operate. The implementation of the calibration technique in the pipelined ADC is investigated. Simulation results show that 109dB of SNDR, 112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall accuracy of the ADC is 18 bits. / Graduation date: 2003

Oversampling and noise-shaping methods for digital-to-analog (D/A) conversion have been widely accepted as methods of choice in high performance data conversion applications. In this thesis, the fundamentals of D/A conversion and oversampling D/A conversion were discussed, along with the detailed analysis and comparison of the reported state-of-the-art oversampling D/A converters. Conventional oversampling D/A converters use 1-bit internal D/A conversion. Complex analog filters and/or large oversampling ratios are usually needed in these 1-bit oversampling D/A converters. Using multi-bit internal D/A conversion, the analog filter can be much simpler and the oversampling ratio can be greatly reduced. However, the linearity of the multi-bit D/A converter has to be at least the same as that required by the overall system. The dual-quantization technique developed in the course of this research provides a good alternative for implementing multi-bit oversampling D/A converters. The system uses two internal D/A converters; one is single-bit and the other is multi-bit. The single-bit D/A converter is used in a path called the signal path while the multi-bit D/A converter is used in a path called the correction path. Since the multi-bit D/A converter is not directly placed in the signal path, its nonlinearity error can be noise shaped by an analog differentiator so that the in-band noise contribution from the nonlinearity error is very small at the system output, greatly reducing the linearity requirement on the multi-bit internal D/A converter. An experimental implementation of an oversampling D/A converter using the dual-quantization technique was carried out to verify the concept. Despite about 10 dB higher noise than expected and the high second-order harmonic distortion due to practical problems in the implementation, the implemented system showed that the corrected output had more than 20 dB improvement over the uncorrected output in both signal-to-noise ratio and dynamic range, demonstrating the validity of the concept. / Graduation date: 1996