Thesis (M.S.)--University of California, Santa Cruz, 1996. / Typescript. Includes bibliographical references.

A computação paralela tem se estabelecido como uma ferramenta indispensável para conseguir o desempenho esperado em aplicações de muitas áreas científicas. É importante avaliar os fatores que limitam o desempenho de uma aplicação paralela. Este trabalho vem apresentar o desenvolvimento e a implementação de uma ferramenta chamada Hierarchical Analyses que permite o levantamento de dados para análise de fatores de desempenho em programas paralelos de forma hierárquica, ou seja, permite coletar as informações acompanhando o nível de abstração usado pelo programador. Essa ferramenta é composta pelos módulos de coleta e transformação dos dados. O módulo de coleta chamado HieraCollector é responsável por coletar e armazenar os dados em arquivos no formato XML, sendo que o usuário não precisa alterar o código fonte de sua aplicação. O módulo de transformação chamado HieraTransform é reponsável por transformar os dados coletados extraindo medidas que permitam a realização da análise do programa paralelo. Para validação dos módulos de coleta e transformação foi utilizada a biblioteca MPI e o framework OOPS que utiliza orientação a objetos. Outra contribuição deste trabalho, foi o desenvolvimento da ferramenta visual chamada HieraOLAP que auxilia o usuário na análise de desempenho de programas paralelos. / Parallel computing has become an essential tool to achieve the performance needed by many scientific applications. The evaluation of performance factors of parallel applications is of utmost significant. This work presents the developement and implementation of a tool called Hierarchical Analyses which facilitates data collection for performance analysis of parallel programs with hierarchical information, i.e. the information is collected in the various abstraction levels used in the application program. The tool consists of a collection and a transformation modules. The collection module (HieraCollector) collects the data and stores it in XML format. The transformation module (HieraTransform) processes the collected data computing measurements to be used in the analysis of parallel code. To validate the tool, implementations adapted to MPI and the OOPS framework have been developed. Another contribution of this work is the development of a visual tool called HieraOLAP to help the user in the analysis of parallel program performance.

This thesis investigates the building of a textual tracing language that operates at the model level to allow trace specification of textually modeled UML constructs. Current tracing approaches focus on manually injecting tracepoints into targeted systems at the source code level. Such approaches are useful in code-centric development styles where the majority of the code is handwritten. However, in the case of Model Driven Development (MDD), where models are utilized to generate some or all of the code, current tracing technology results in low level trace specification and generation of execution traces that are not aware of or linked to the originating model-level constructs. Dynamic analysis hence becomes harder for a modeler adopting an MDD approach. This field, which we call model-oriented tracing, is currently immature, with little pre-existing research. In this thesis, we present a textual model-level tracing language, implemented as part of Umple, that overcomes some of the limitations of existing tracing methods. The language facilitates model-level tracing, in a fashion very similar to code tracing. The language, which we call MOTL (Model-Oriented Tracing Language) allows tracing of UML associations, attributes and state machines. Constraints can be imposed to limit the scope of tracing. As a result of this work, modelers will gain the ability to specify traces of UML constructs at the model level without the need to modify the generated code, and then generate execution traces when the generated system is run. The resulting trace links back to the model constructs. Modelers can choose from among several tracing technologies including basic file or console output, Java logging framework, Log4J and LTTng. This thesis defines the language syntactically and semantically. Model-Driven Development (MDD) and Test-Driven Development (TDD) were followed to implement the language architecture to ensure high quality code generation. MOTL was used in the development in two of Umple subprojects. An empirical evaluation was conducted to evaluate the language’s usability.

An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing the number of signals traced and maximizing the observability/restorability of other untraced signals during post-silicon validation. In this thesis, a new method is proposed for trace buffer signal selection for the purpose of post-silicon debug. The selection is performed by favoring those signals with the most number of implications that are not implied by other signals. Then, based on the values of the traced signals during silicon debug, an algorithm which uses a SAT-based multi-node implication engine is introduced to restore the values of untraced signals across multiple time-frames. A new multiplexer-based trace signal interconnection scheme and a new heuristic for trace signal selection based on implication-based correlation are also described. By this approach, we can effectively trace twice as many signals with the same trace buffer width. A SAT-based greedy heuristic is also proposed to prune the selected trace signal list further to take into account those multi-node implications. A state restoration algorithm is developed for the multiplexer-based trace signal interconnection scheme. Experimental results show that the proposed approaches select the trace signals effectively, giving a high restoration percentage compared with other techniques. We finally propose a lossless compression technique to increase the capacity of the trace buffer. We propose real-time compression of the trace data using Frequency-Directed Run-Length (FDR) code. In addition, we also propose source transformation functions, namely difference vector computation, efficient ordering of trace flip-flops and alternate vector reversal that reduces the entropy of the trace data, making them more amenable for compression. The order of the trace flip-flops is computed off-chip using a probabilistic algorithm. The difference vector computation and alternate vector reversal are implemented on-chip and incurs negligible hardware overhead. Experimental results for sequential benchmark circuits shows that this method gives a better compression percentage compared to dictionary-based techniques and yields up to 3X improvement in the diagnostic capability. We also observe that the area overhead of the proposed approach is less compared to dictionary-based compression techniques. / Master of Science

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