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This thesis deals with computer generated images. The thesis begins with an overview of a generalised computer graphics system, including a brief survey of typical methods for generating photorealistic images. One such technique, ray tracing, is used as the basis for the work which follows. The overview section concludes with a statement of the aim which is to: Investigate the effective use of available processing power and effective utilisation of available memory by implementing a ray tracing programme which uses space subdivision, multiple processors and a distributed world model database. The problem formulation section describes the ray tracing principle and then introduces the main areas of study. The INMOS Transputer (a building block for concurrent systems) is used to implement the multiple process ray tracer. Space subdivision is achieved by repeated and regular subdivision of a world cube (which contains the scene to be ray traced) into named cubes, called octrees. The subdivision algorithm continues to subdivide space until no octree contains more than a specified number of objects, or until the practical limit of space subdivision is reached. The objects in the world model database are distributed in a round robin manner to the ray trace processes. During execution of the ray trace programme, information about each object is passed between processes by a message mechanism. The concurrent code for the transputer processes, written in OCCAM 2, was developed using timing diagrams and signal flow diagrams derived by analogy from digital electronics. Structure diagrams, modified to be consistent with OCCAM 2 processes, were derived from the timing diagrams and signal flow diagrams. These were used as a basis for the coding. The results show that space subdivision is an effective use of processor power because the number of trial intersections of rays with objects is dramatically reduced. In addition, distribution of the world model database avoids duplication of the database in the memory of each process and hence better utilisation of available memory is achieved. The programmes are supported by a menu driven interface (running on a PC AT) which enables the user to control the ray trace processes running on the transputer board housed in the PC.

Recently, methods were developed to render various global illumination effects with rasterization GPUs. Among those were hardware based ray tracing and photon mapping. However, due to current GPU??s inherent architectural limitations, the efficiency and throughput of these methods remained low. In this thesis, we propose a coherent rendering system that addresses these issues. First, we introduce new photon mapping and ray racing acceleration algorithms that facilitate data coherence and spatial locality, as well as eliminating unnecessary random memory accesses. A high level abstraction of the combined ray tracing and photon mapping streaming pipeline is introduced. Based on this abstraction, an efficient ray tracing and photon mapping GPU is designed. Using an event driven simulator, developed for this GPU, we verify and validate the proposed algorithms and architecture. Simulation results have validated better interactive performances compared to the current GPUs.

The influence of elastic anisotropy on seismic wave propagation is often neglected for the sake of simplicity. However, ignoring anisotropy may lead to significant errors in the processing of seismic data and ultimately in a poor image of the subsurface. This is especially true in wide-aperture Vertical Seismic Profiles where waves travel both vertically and horizontally. Anisotropy has been neglected in wavefront construction methods of seismic ray-tracing until Gibson (2000), who showed they are powerful tools to simulate seismic wave propagation in three-dimensional anisotropic subsurface models. The code is currently under development using a C++ object oriented programming approach because it provides high flexibility in the design of new components and facilitates debugging and maintenance of a complex algorithm. So far, the code was used to simulate propagation in homogeneous or simple heterogeneous anisotropic velocity models mainly designed for testing purposes. In particular, it has never been applied to simulate a field dataset. We propose here an analytical method involving little algebra and that allows the design of realistic heterogeneous anisotropic models using the C++ object oriented programming approach. The new model class can model smooth multi-layered subsurface with gradients or models with many dip variations. It has been used to model first arrival times of a wide-aperture VSP dataset from the Gulf of Mexico to estimate the amount of anisotropy. The proposed velocity model is transversely isotropic. The anisotropy is constant throughout the model and is defined via Thomsen's parameters. Values in the final model are epsilon = 0.055 and delta = -0.115. The model is compatible with the a priori knowledge of the local geology and reduces the RMS average time difference between measured and computed travel times by 51% in comparison to the initial isotropic model. These values are realistic and are similar to other measurements of anisotropy in the Gulf of Mexico.

In diesem Beitrag lesen Sie: • was unter innerbetrieblicher Logistik verstanden werden kann, • wie ERP- und PPS Systeme Funktionen der innerbetrieblichen Logistik erfüllen, • welche zukunftsorientierten Technologien durch diese Systeme unterstützt werden.

In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it¡¦s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead. Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1). For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.

It was hypothesized that superparamagnetic nanoparticles encapsulated in a silica shell with a fluorescent dye could be functionalized with axonal tracers and could be used for serial, non-invasive imaging with magnetic resonance imaging (MRI) for axon tract tracing. Nanoparticles functionalized with amine, octadecyl, silica, and biotinylated dextran amine were manufactured and characterized with MRI, scanning electron microscopy, and UV-visible, infrared, and fluorescence spectroscopy. Nanoparticle concentrations of 10 mM were not toxic to adult rat neural progenitor cells (NPCs) and labeled approximately 90% of cells. Nanoparticles were assessed for anterograde and retrograde tract tracing in adult rat models. With MRI and microscopy, the nanoparticles did not appear to trace axons but did provide an MRI signal for up to 3 weeks post implantation. While functionalized nanoparticles did not appear to trace axons, they are not toxic to NPCs and may be used as a MRI contrast agent in the neural axis.

It was hypothesized that superparamagnetic nanoparticles encapsulated in a silica shell with a fluorescent dye could be functionalized with axonal tracers and could be used for serial, non-invasive imaging with magnetic resonance imaging (MRI) for axon tract tracing. Nanoparticles functionalized with amine, octadecyl, silica, and biotinylated dextran amine were manufactured and characterized with MRI, scanning electron microscopy, and UV-visible, infrared, and fluorescence spectroscopy. Nanoparticle concentrations of 10 mM were not toxic to adult rat neural progenitor cells (NPCs) and labeled approximately 90% of cells. Nanoparticles were assessed for anterograde and retrograde tract tracing in adult rat models. With MRI and microscopy, the nanoparticles did not appear to trace axons but did provide an MRI signal for up to 3 weeks post implantation. While functionalized nanoparticles did not appear to trace axons, they are not toxic to NPCs and may be used as a MRI contrast agent in the neural axis.

In the past, ray tracing has been used widely in offline rendering applications since it provided the ability to better capture high quality secondary effects such as reflection, refraction and shadows. Such effects are difficult to produce in a robust, high quality fashion with traditional, real-time rasterization algorithms. Motivated to bring the advantages to ray tracing to real-time applications, researchers have developed better and more efficient algorithms that leverage the current generation of fast, parallel CPU hardware within the past few years. This thesis provides the implementation and design details of a high performance ray tracing solution called ``RTTest'' for standard, desktop CPUs. Background information on various algorithms and acceleration structures are first discussed followed by an introduction to novel techniques used to better accelerate current, core ray tracing techniques. Techniques such as Omni-Directional Packets, Cone Proxy Traversal and Multiple Frustum Traversal are proposed and benchmarked using standard ray tracing scenes. Also, a novel soft shadowing algorithm called Edge Width Soft Shadows is proposed which achieves performance comparable to a single sampled hard shadow approach targeted at real time applications such as games. Finally, additional information on the memory layout, rendering pipeline, shader system and code level optimizations of RTTest are also discussed.

CAD objects are geometrical descriptions of physical scenes from the real world. Ray tracing is used to project the objects onto a pixel screen. A lit and a shadow zone are formed according to the direction of the incoming field (light) and the orientation of the pixel screen. The arc length along the surface of the object, from the shadow boundary to a point in the lit zone, is computed by means of numerical integration. The arclengths corresponding to two orthogonal directions that are aligned with the pixels on the pixel screen are computed and used for interpolation to obtain the arc length for all directions. A number of simulations for various CAD geometries are made using a ray-tracer implemented in FORTRAN 90.