Graduation date: 1994

Thesis (Ph.D.)--Stanford University, 2006. / Adviser: Krishna C. Saraswat. Includes bibliographical references (p. 160-177)

Not available

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 159-164).

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references. Also available on the World Wide Web.

Hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) are used as switching elements in large area active matrix liquid crystal displays and various image sensing devices for radiation detection. The noise inherent in the a-Si:H TFTs contributes to the overall noise figure of such devices and degrades the signal to noise ratio; therefore, the noise is an important factor in the design of the devices. The noise of the a-Si:H TFTs has been studied experimentally, but the origin of the noise is not understood. <p> This work calculates the noise of the a-Si:H TFTs based on a simulation of operation of the TFTs and the hypothesis that the device noise is due to the intrinsic noise of the a-Si:H material. An a-Si:H TFT with an inverted-staggered structure has been simulated by numerically solving the fundamental transport equations for various gate and drain-source voltages. The drain-source curves derived from the simulation agree qualitatively with the experimental results: both the linear and saturated regions are observed. The low frequency noise was calculated based on the charge density distribution in the channel obtained from the simulation and the known dependence of the noise in the a-Si:H on the charge density, Hooges relation. The calculated noise power increases with the drain-source voltage and is inversely proportional to the gate voltage or the effective channel length. The curves agree qualitatively with the experimental results. The calculated noise power agrees quantitatively with the experiments when the scaling parameter in Hooges relation, , is set to . This value agrees with the experimentally determined value for a-Si:H. The results are consistent with the hypothesis that the low frequency noise in the a-Si:H TFTs is due to the material itself.

Graduation date: 1990

Hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) are used as switching elements in large area active matrix liquid crystal displays and various image sensing devices for radiation detection. The noise inherent in the a-Si:H TFTs contributes to the overall noise figure of such devices and degrades the signal to noise ratio; therefore, the noise is an important factor in the design of the devices. The noise of the a-Si:H TFTs has been studied experimentally, but the origin of the noise is not understood. <p> This work calculates the noise of the a-Si:H TFTs based on a simulation of operation of the TFTs and the hypothesis that the device noise is due to the intrinsic noise of the a-Si:H material. An a-Si:H TFT with an inverted-staggered structure has been simulated by numerically solving the fundamental transport equations for various gate and drain-source voltages. The drain-source curves derived from the simulation agree qualitatively with the experimental results: both the linear and saturated regions are observed. The low frequency noise was calculated based on the charge density distribution in the channel obtained from the simulation and the known dependence of the noise in the a-Si:H on the charge density, Hooges relation. The calculated noise power increases with the drain-source voltage and is inversely proportional to the gate voltage or the effective channel length. The curves agree qualitatively with the experimental results. The calculated noise power agrees quantitatively with the experiments when the scaling parameter in Hooges relation, , is set to . This value agrees with the experimentally determined value for a-Si:H. The results are consistent with the hypothesis that the low frequency noise in the a-Si:H TFTs is due to the material itself.

In this thesis, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure. In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits. Otherwise, we have investigated the mechanism of the leakage currents in polysilicon TFT with different temperature and applied biases. Moreover, we have simulated the electric fields in different structure polysilicon TFT to explain the mechanism of the leakage currents. By comparing the leakage currents in different channel structures, the leakage current in nanowire channel structure is higher than that in non-nanowire channel structure. Moreover, the leakage current in multiple gate structure is lower than that in single gate structure. Therefore, these two experimental results are caused by high electric field in the drain-to-gate overlap and drain-to-body depletion region respectively.

Thèse de doctorat : SCIENCES ET TECHNIQUES : Metz : 1999. / 1999METZ030S. 60 ref.